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https://github.com/ARM-software/arm-trusted-firmware.git
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ab2d31edbd
- Add instructions for contributing to ARM Trusted Firmware. - Update copyright text in all files to acknowledge contributors. Change-Id: I9311aac81b00c6c167d2f8c889aea403b84450e5
233 lines
5.8 KiB
ArmAsm
233 lines
5.8 KiB
ArmAsm
/*
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* Copyright (c) 2013, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch_helpers.h>
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#include <asm_macros.S>
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.globl dcisw
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.globl dccisw
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.globl dccsw
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.globl dccvac
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.globl dcivac
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.globl dccivac
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.globl dccvau
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.globl dczva
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.globl flush_dcache_range
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.globl inv_dcache_range
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.globl dcsw_op_louis
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.globl dcsw_op_all
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.section .text, "ax"; .align 3
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dcisw:; .type dcisw, %function
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dc isw, x0
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dsb sy
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isb
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ret
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dccisw:; .type dccisw, %function
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dc cisw, x0
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dsb sy
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isb
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ret
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dccsw:; .type dccsw, %function
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dc csw, x0
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dsb sy
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isb
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ret
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dccvac:; .type dccvac, %function
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dc cvac, x0
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dsb sy
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isb
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ret
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dcivac:; .type dcivac, %function
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dc ivac, x0
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dsb sy
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isb
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ret
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dccivac:; .type dccivac, %function
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dc civac, x0
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dsb sy
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isb
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ret
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dccvau:; .type dccvau, %function
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dc cvau, x0
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dsb sy
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isb
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ret
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dczva:; .type dczva, %function
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dc zva, x0
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dsb sy
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isb
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ret
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/* ------------------------------------------
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* Clean+Invalidate from base address till
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* size. 'x0' = addr, 'x1' = size
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* ------------------------------------------
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*/
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flush_dcache_range:; .type flush_dcache_range, %function
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dcache_line_size x2, x3
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add x1, x0, x1
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sub x3, x2, #1
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bic x0, x0, x3
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flush_loop:
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dc civac, x0
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add x0, x0, x2
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cmp x0, x1
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b.lo flush_loop
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dsb sy
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ret
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/* ------------------------------------------
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* Invalidate from base address till
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* size. 'x0' = addr, 'x1' = size
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* ------------------------------------------
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*/
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inv_dcache_range:; .type inv_dcache_range, %function
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dcache_line_size x2, x3
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add x1, x0, x1
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sub x3, x2, #1
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bic x0, x0, x3
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inv_loop:
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dc ivac, x0
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add x0, x0, x2
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cmp x0, x1
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b.lo inv_loop
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dsb sy
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ret
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/* ------------------------------------------
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* Data cache operations by set/way to the
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* level specified
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* ------------------------------------------
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* ----------------------------------
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* Call this func with the clidr in
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* x0, starting cache level in x10,
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* last cache level in x3 & cm op in
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* x14
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* ----------------------------------
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*/
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dcsw_op:; .type dcsw_op, %function
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all_start_at_level:
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add x2, x10, x10, lsr #1 // work out 3x current cache level
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lsr x1, x0, x2 // extract cache type bits from clidr
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and x1, x1, #7 // mask of the bits for current cache only
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cmp x1, #2 // see what cache we have at this level
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b.lt skip // skip if no cache, or just i-cache
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msr csselr_el1, x10 // select current cache level in csselr
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isb // isb to sych the new cssr&csidr
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mrs x1, ccsidr_el1 // read the new ccsidr
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and x2, x1, #7 // extract the length of the cache lines
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add x2, x2, #4 // add 4 (line length offset)
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mov x4, #0x3ff
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and x4, x4, x1, lsr #3 // find maximum number on the way size
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clz w5, w4 // find bit position of way size increment
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mov x7, #0x7fff
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and x7, x7, x1, lsr #13 // extract max number of the index size
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loop2:
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mov x9, x4 // create working copy of max way size
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loop3:
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lsl x6, x9, x5
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orr x11, x10, x6 // factor way and cache number into x11
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lsl x6, x7, x2
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orr x11, x11, x6 // factor index number into x11
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mov x12, x0
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mov x13, x30 // lr
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mov x0, x11
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blr x14
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mov x0, x12
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mov x30, x13 // lr
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subs x9, x9, #1 // decrement the way
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b.ge loop3
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subs x7, x7, #1 // decrement the index
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b.ge loop2
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skip:
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add x10, x10, #2 // increment cache number
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cmp x3, x10
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b.gt all_start_at_level
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finished:
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mov x10, #0 // swith back to cache level 0
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msr csselr_el1, x10 // select current cache level in csselr
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dsb sy
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isb
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ret
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do_dcsw_op:; .type do_dcsw_op, %function
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cbz x3, exit
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cmp x0, #DCISW
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b.eq dc_isw
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cmp x0, #DCCISW
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b.eq dc_cisw
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cmp x0, #DCCSW
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b.eq dc_csw
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dc_isw:
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mov x0, x9
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adr x14, dcisw
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b dcsw_op
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dc_cisw:
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mov x0, x9
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adr x14, dccisw
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b dcsw_op
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dc_csw:
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mov x0, x9
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adr x14, dccsw
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b dcsw_op
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exit:
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ret
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dcsw_op_louis:; .type dcsw_op_louis, %function
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dsb sy
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setup_dcsw_op_args x10, x3, x9, #LOUIS_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT
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b do_dcsw_op
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dcsw_op_all:; .type dcsw_op_all, %function
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dsb sy
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setup_dcsw_op_args x10, x3, x9, #LOC_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT
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b do_dcsw_op
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