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7b41acaf72
EXTLLC bit in CPUECTLR_EL1(for non-gelas cpus) and in CPUECTLR2_EL1 register for gelas cpu enables external Last-level cache in the system, External LLC is present on TC4 systems in MCN but it is not enabled in CPU registers so enable it. On TC4, Gelas vs Non-Gelas CPUs have different bits to enable EXTLLC so take care of that as well. Change-Id: Ic6a74b4af110a3c34d19131676e51901ea2bf6e3 Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com> Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
32 lines
1.1 KiB
C
32 lines
1.1 KiB
C
/*
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* Copyright (c) 2023, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_GELAS_H
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#define CORTEX_GELAS_H
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#include <lib/utils_def.h>
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#define CORTEX_GELAS_MIDR U(0x410FD8B0)
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/*******************************************************************************
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* CPU Extended Control register specific definitions
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******************************************************************************/
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#define CORTEX_GELAS_IMP_CPUECTLR_EL1 S3_0_C15_C1_5
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#define CPUECTLR2_EL1_EXTLLC_BIT 10
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_GELAS_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_GELAS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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/*******************************************************************************
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* SME Control registers
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******************************************************************************/
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#define CORTEX_GELAS_SVCRSM S0_3_C4_C2_3
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#define CORTEX_GELAS_SVCRZA S0_3_C4_C4_3
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#endif /* CORTEX_GELAS_H */
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