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e5b0664ce7
This patch locks access to the PMC registers which hold the CPU reset vector addresses. The PMC registers are used by the warmboot code and must be locked during boot/resume to avoid booting into custom firmware installed by unknown parties e.g. hackers. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
64 lines
2.5 KiB
C
64 lines
2.5 KiB
C
/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <debug.h>
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#include <mmio.h>
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#include <pmc.h>
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#include <tegra_def.h>
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#define SB_CSR 0x0
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#define SB_CSR_NS_RST_VEC_WR_DIS (1 << 1)
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/* CPU reset vector */
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#define SB_AA64_RESET_LOW 0x30 /* width = 31:0 */
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#define SB_AA64_RESET_HI 0x34 /* width = 11:0 */
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extern void tegra_secure_entrypoint(void);
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/*******************************************************************************
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* Setup secondary CPU vectors
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******************************************************************************/
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void plat_secondary_setup(void)
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{
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uint32_t val;
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uint64_t reset_addr = (uint64_t)tegra_secure_entrypoint;
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INFO("Setting up secondary CPU boot\n");
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/* setup secondary CPU vector */
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mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_LOW,
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(reset_addr & 0xFFFFFFFF) | 1);
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val = reset_addr >> 32;
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mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_HI, val & 0x7FF);
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/* configure PMC */
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tegra_pmc_cpu_setup(reset_addr);
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tegra_pmc_lock_cpu_vectors();
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}
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