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https://github.com/ARM-software/arm-trusted-firmware.git
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dc7fdad251
This patch adds support to run a Trusted OS during boot time. The previous stage bootloader passes the entry point information in the 'bl32_ep_info' structure, which is passed over to the SPD. The build system expects the dispatcher to be passed as an input parameter using the 'SPD=<dispatcher>' option. The Tegra docs have also been updated with this information. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
93 lines
3.9 KiB
C
93 lines
3.9 KiB
C
/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __PLATFORM_DEF_H__
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#define __PLATFORM_DEF_H__
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#include <arch.h>
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#include <common_def.h>
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/*******************************************************************************
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* Generic platform constants
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******************************************************************************/
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/* Size of cacheable stacks */
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#if DEBUG_XLAT_TABLE
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#define PLATFORM_STACK_SIZE 0x800
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#elif IMAGE_BL31
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#define PLATFORM_STACK_SIZE 0x400
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#endif
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#define TEGRA_PRIMARY_CPU 0x0
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#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2
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#define PLATFORM_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
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#define PLATFORM_NUM_AFFS ((PLATFORM_CLUSTER_COUNT * \
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PLATFORM_CORE_COUNT) + \
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PLATFORM_CLUSTER_COUNT + 1)
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/*******************************************************************************
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* Platform console related constants
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******************************************************************************/
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#define TEGRA_CONSOLE_BAUDRATE 115200
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#define TEGRA_BOOT_UART_CLK_IN_HZ 408000000
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/*******************************************************************************
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* Platform memory map related constants
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******************************************************************************/
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/* Size of trusted dram */
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#define TZDRAM_SIZE 0x00400000
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#define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE)
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/*******************************************************************************
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* BL31 specific defines.
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******************************************************************************/
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#define BL31_SIZE 0x20000
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#define BL31_BASE TZDRAM_BASE
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#define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1)
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#define BL32_BASE (TZDRAM_BASE + BL31_SIZE)
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#define BL32_LIMIT TZDRAM_END
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/*******************************************************************************
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* Platform specific page table and MMU setup constants
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******************************************************************************/
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#define ADDR_SPACE_SIZE (1ull << 32)
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#define MAX_XLAT_TABLES 3
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#define MAX_MMAP_REGIONS 8
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/*******************************************************************************
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* Some data must be aligned on the biggest cache line size in the platform.
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* This is known only to the platform as it might have a combination of
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* integrated and external caches.
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******************************************************************************/
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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#endif /* __PLATFORM_DEF_H__ */
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