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https://github.com/ARM-software/arm-trusted-firmware.git
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08438e24e1
T210 is the latest chip in the Tegra family of SoCs from NVIDIA. It is an ARM v8 dual-cluster (A57/A53) SoC, with any one of the clusters being active at a given point in time. This patch adds support to boot the Trusted Firmware on T210 SoCs. The patch also adds support to boot secondary CPUs, enter/exit core power states for all CPUs in the slow/fast clusters. The support to switch between clusters is still not available in this patch and would be available later. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
94 lines
3 KiB
ArmAsm
94 lines
3 KiB
ArmAsm
/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __PLAT_MACROS_S__
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#define __PLAT_MACROS_S__
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#include <gic_v2.h>
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#include <tegra_def.h>
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.section .rodata.gic_reg_name, "aS"
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gicc_regs:
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.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
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gicd_pend_reg:
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.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
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newline:
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.asciz "\n"
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spacer:
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.asciz ":\t\t0x"
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/* ---------------------------------------------
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* The below macro prints out relevant GIC
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* registers whenever an unhandled exception is
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* taken in BL31.
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* ---------------------------------------------
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*/
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.macro plat_print_gic_regs
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mov_imm x16, TEGRA_GICC_BASE
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cbz x16, 1f
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/* gicc base address is now in x16 */
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adr x6, gicc_regs /* Load the gicc reg list to x6 */
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/* Load the gicc regs to gp regs used by str_in_crash_buf_print */
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ldr w8, [x16, #GICC_HPPIR]
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ldr w9, [x16, #GICC_AHPPIR]
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ldr w10, [x16, #GICC_CTLR]
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/* Store to the crash buf and print to cosole */
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bl str_in_crash_buf_print
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/* Print the GICD_ISPENDR regs */
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add x7, x16, #GICD_ISPENDR
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adr x4, gicd_pend_reg
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bl asm_print_str
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2:
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sub x4, x7, x16
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cmp x4, #0x280
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b.eq 1f
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bl asm_print_hex
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adr x4, spacer
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bl asm_print_str
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ldr x4, [x7], #8
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bl asm_print_hex
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adr x4, newline
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bl asm_print_str
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b 2b
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1:
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.endm
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/* ------------------------------------------------
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* The below required platform porting macro prints
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* out relevant interconnect registers whenever an
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* unhandled exception is taken in BL3-1.
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* ------------------------------------------------
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*/
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.macro plat_print_interconnect_regs
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nop
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.endm
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#endif /* __PLAT_MACROS_S__ */
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