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https://github.com/ARM-software/arm-trusted-firmware.git
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08438e24e1
T210 is the latest chip in the Tegra family of SoCs from NVIDIA. It is an ARM v8 dual-cluster (A57/A53) SoC, with any one of the clusters being active at a given point in time. This patch adds support to boot the Trusted Firmware on T210 SoCs. The patch also adds support to boot secondary CPUs, enter/exit core power states for all CPUs in the slow/fast clusters. The support to switch between clusters is still not available in this patch and would be available later. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
85 lines
3.2 KiB
C
85 lines
3.2 KiB
C
/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __FLOWCTRL_H__
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#define __FLOWCTRL_H__
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#include <mmio.h>
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#include <tegra_def.h>
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#define FLOWCTRL_HALT_CPU0_EVENTS 0x0
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#define FLOWCTRL_WAITEVENT (2 << 29)
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#define FLOWCTRL_WAIT_FOR_INTERRUPT (4 << 29)
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#define FLOWCTRL_JTAG_RESUME (1 << 28)
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#define FLOWCTRL_HALT_SCLK (1 << 27)
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#define FLOWCTRL_HALT_LIC_IRQ (1 << 11)
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#define FLOWCTRL_HALT_LIC_FIQ (1 << 10)
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#define FLOWCTRL_HALT_GIC_IRQ (1 << 9)
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#define FLOWCTRL_HALT_GIC_FIQ (1 << 8)
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#define FLOWCTRL_HALT_BPMP_EVENTS 0x4
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#define FLOWCTRL_CPU0_CSR 0x8
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#define FLOW_CTRL_CSR_PWR_OFF_STS (1 << 16)
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#define FLOWCTRL_CSR_INTR_FLAG (1 << 15)
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#define FLOWCTRL_CSR_EVENT_FLAG (1 << 14)
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#define FLOWCTRL_CSR_IMMEDIATE_WAKE (1 << 3)
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#define FLOWCTRL_CSR_ENABLE (1 << 0)
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#define FLOWCTRL_HALT_CPU1_EVENTS 0x14
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#define FLOWCTRL_CPU1_CSR 0x18
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#define FLOWCTRL_CC4_CORE0_CTRL 0x6c
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#define FLOWCTRL_WAIT_WFI_BITMAP 0x100
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#define FLOWCTRL_L2_FLUSH_CONTROL 0x94
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#define FLOWCTRL_BPMP_CLUSTER_CONTROL 0x98
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#define FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK (1 << 2)
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#define FLOWCTRL_ENABLE_EXT 12
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#define FLOWCTRL_ENABLE_EXT_MASK 3
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#define FLOWCTRL_PG_CPU_NONCPU 0x1
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#define FLOWCTRL_TURNOFF_CPURAIL 0x2
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static inline uint32_t tegra_fc_read_32(uint32_t off)
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{
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return mmio_read_32(TEGRA_FLOWCTRL_BASE + off);
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}
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static inline void tegra_fc_write_32(uint32_t off, uint32_t val)
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{
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mmio_write_32(TEGRA_FLOWCTRL_BASE + off, val);
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}
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void tegra_fc_cpu_idle(uint32_t mpidr);
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void tegra_fc_cluster_idle(uint32_t midr);
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void tegra_fc_cluster_powerdn(uint32_t midr);
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void tegra_fc_soc_powerdn(uint32_t midr);
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void tegra_fc_cpu_on(int cpu);
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void tegra_fc_cpu_off(int cpu);
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void tegra_fc_lock_active_cluster(void);
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void tegra_fc_reset_bpmp(void);
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#endif /* __FLOWCTRL_H__ */
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