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93eafbcad4
The validate_power_state() handler checks the power_state for a valid afflvl and state id. Although the afflvl check is common, the state ids are implementation defined. This patch moves the handler to the tegra/soc folder to allow each SoC to validate the power_state for supported parameters. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
339 lines
11 KiB
C
339 lines
11 KiB
C
/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <context.h>
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#include <context_mgmt.h>
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#include <debug.h>
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#include <memctrl.h>
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#include <mmio.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <pmc.h>
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#include <psci.h>
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#include <tegra_def.h>
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#include <tegra_private.h>
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extern uint64_t tegra_bl31_phys_base;
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extern uint64_t sec_entry_point[PLATFORM_CORE_COUNT];
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static int system_suspended;
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/*
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* The following platform setup functions are weakly defined. They
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* provide typical implementations that will be overridden by a SoC.
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*/
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#pragma weak tegra_soc_prepare_cpu_suspend
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#pragma weak tegra_soc_prepare_cpu_on
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#pragma weak tegra_soc_prepare_cpu_off
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#pragma weak tegra_soc_prepare_cpu_on_finish
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int tegra_soc_prepare_cpu_suspend(unsigned int id, unsigned int afflvl)
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{
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return PSCI_E_NOT_SUPPORTED;
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}
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int tegra_soc_prepare_cpu_on(unsigned long mpidr)
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{
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_prepare_cpu_off(unsigned long mpidr)
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{
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_prepare_cpu_on_finish(unsigned long mpidr)
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{
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return PSCI_E_SUCCESS;
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}
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/*******************************************************************************
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* Track system suspend entry.
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******************************************************************************/
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void tegra_pm_system_suspend_entry(void)
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{
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system_suspended = 1;
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}
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/*******************************************************************************
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* Track system suspend exit.
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******************************************************************************/
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void tegra_pm_system_suspend_exit(void)
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{
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system_suspended = 0;
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}
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/*******************************************************************************
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* Get the system suspend state.
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******************************************************************************/
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int tegra_system_suspended(void)
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{
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return system_suspended;
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}
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/*******************************************************************************
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* Handler called when an affinity instance is about to enter standby.
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******************************************************************************/
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void tegra_affinst_standby(unsigned int power_state)
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{
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/*
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* Enter standby state
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* dsb is good practice before using wfi to enter low power states
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*/
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dsb();
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wfi();
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}
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/*******************************************************************************
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* This handler is called by the PSCI implementation during the `SYSTEM_SUSPEND`
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* call to get the `power_state` parameter. This allows the platform to encode
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* the appropriate State-ID field within the `power_state` parameter which can
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* be utilized in `affinst_suspend()` to suspend to system affinity level.
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******************************************************************************/
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unsigned int tegra_get_sys_suspend_power_state(void)
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{
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unsigned int power_state;
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power_state = psci_make_powerstate(PLAT_SYS_SUSPEND_STATE_ID,
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PSTATE_TYPE_POWERDOWN, MPIDR_AFFLVL2);
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return power_state;
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}
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/*******************************************************************************
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* Handler called to check the validity of the power state parameter.
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******************************************************************************/
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int32_t tegra_validate_power_state(unsigned int power_state)
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{
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return tegra_soc_validate_power_state(power_state);
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}
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/*******************************************************************************
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* Handler called when an affinity instance is about to be turned on. The
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* level and mpidr determine the affinity instance.
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******************************************************************************/
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int tegra_affinst_on(unsigned long mpidr,
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unsigned long sec_entrypoint,
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unsigned int afflvl,
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unsigned int state)
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{
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int cpu = mpidr & MPIDR_CPU_MASK;
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/*
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* Support individual CPU power on only.
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*/
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if (afflvl > MPIDR_AFFLVL0)
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return PSCI_E_SUCCESS;
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/*
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* Flush entrypoint variable to PoC since it will be
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* accessed after a reset with the caches turned off.
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*/
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sec_entry_point[cpu] = sec_entrypoint;
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flush_dcache_range((uint64_t)&sec_entry_point[cpu], sizeof(uint64_t));
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return tegra_soc_prepare_cpu_on(mpidr);
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}
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/*******************************************************************************
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* Handler called when an affinity instance is about to be turned off. The
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* level determines the affinity instance. The 'state' arg. allows the
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* platform to decide whether the cluster is being turned off and take apt
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* actions.
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*
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* CAUTION: This function is called with coherent stacks so that caches can be
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* turned off, flushed and coherency disabled. There is no guarantee that caches
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* will remain turned on across calls to this function as each affinity level is
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* dealt with. So do not write & read global variables across calls. It will be
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* wise to do flush a write to the global to prevent unpredictable results.
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******************************************************************************/
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void tegra_affinst_off(unsigned int afflvl, unsigned int state)
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{
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/*
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* Support individual CPU power off only.
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*/
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if (afflvl > MPIDR_AFFLVL0)
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return;
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tegra_soc_prepare_cpu_off(read_mpidr());
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}
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/*******************************************************************************
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* Handler called when an affinity instance is about to be suspended. The
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* level and mpidr determine the affinity instance. The 'state' arg. allows the
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* platform to decide whether the cluster is being turned off and take apt
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* actions.
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*
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* CAUTION: This function is called with coherent stacks so that caches can be
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* turned off, flushed and coherency disabled. There is no guarantee that caches
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* will remain turned on across calls to this function as each affinity level is
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* dealt with. So do not write & read global variables across calls. It will be
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* wise to flush a write to the global variable, to prevent unpredictable
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* results.
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******************************************************************************/
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void tegra_affinst_suspend(unsigned long sec_entrypoint,
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unsigned int afflvl,
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unsigned int state)
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{
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int id = psci_get_suspend_stateid();
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int cpu = read_mpidr() & MPIDR_CPU_MASK;
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if (afflvl > PLATFORM_MAX_AFFLVL)
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return;
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/*
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* Flush entrypoint variable to PoC since it will be
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* accessed after a reset with the caches turned off.
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*/
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sec_entry_point[cpu] = sec_entrypoint;
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flush_dcache_range((uint64_t)&sec_entry_point[cpu], sizeof(uint64_t));
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tegra_soc_prepare_cpu_suspend(id, afflvl);
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/* disable GICC */
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tegra_gic_cpuif_deactivate();
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}
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/*******************************************************************************
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* Handler called when an affinity instance has just been powered on after
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* being turned off earlier. The level determines the affinity instance.
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* The 'state' arg. allows the platform to decide whether the cluster was
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* turned off prior to wakeup and do what's necessary to set it up.
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******************************************************************************/
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void tegra_affinst_on_finish(unsigned int afflvl, unsigned int state)
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{
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plat_params_from_bl2_t *plat_params;
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/*
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* Support individual CPU power on only.
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*/
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if (afflvl > MPIDR_AFFLVL0)
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return;
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/*
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* Initialize the GIC cpu and distributor interfaces
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*/
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tegra_gic_setup();
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/*
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* Check if we are exiting from deep sleep.
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*/
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if (tegra_system_suspended()) {
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/*
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* Lock scratch registers which hold the CPU vectors.
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*/
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tegra_pmc_lock_cpu_vectors();
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/*
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* SMMU configuration.
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*/
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tegra_memctrl_setup();
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/*
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* Security configuration to allow DRAM/device access.
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*/
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plat_params = bl31_get_plat_params();
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tegra_memctrl_tzdram_setup(tegra_bl31_phys_base,
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plat_params->tzdram_size);
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}
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/*
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* Reset hardware settings.
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*/
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tegra_soc_prepare_cpu_on_finish(read_mpidr());
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}
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/*******************************************************************************
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* Handler called when an affinity instance has just been powered on after
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* having been suspended earlier. The level and mpidr determine the affinity
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* instance.
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******************************************************************************/
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void tegra_affinst_suspend_finish(unsigned int afflvl, unsigned int state)
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{
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if (afflvl == MPIDR_AFFLVL0)
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tegra_affinst_on_finish(afflvl, state);
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}
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/*******************************************************************************
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* Handler called when the system wants to be powered off
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******************************************************************************/
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__dead2 void tegra_system_off(void)
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{
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ERROR("Tegra System Off: operation not handled.\n");
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panic();
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}
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/*******************************************************************************
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* Handler called when the system wants to be restarted.
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******************************************************************************/
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__dead2 void tegra_system_reset(void)
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{
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/*
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* Program the PMC in order to restart the system.
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*/
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tegra_pmc_system_reset();
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}
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/*******************************************************************************
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* Export the platform handlers to enable psci to invoke them
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******************************************************************************/
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static const plat_pm_ops_t tegra_plat_pm_ops = {
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.affinst_standby = tegra_affinst_standby,
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.affinst_on = tegra_affinst_on,
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.affinst_off = tegra_affinst_off,
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.affinst_suspend = tegra_affinst_suspend,
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.affinst_on_finish = tegra_affinst_on_finish,
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.affinst_suspend_finish = tegra_affinst_suspend_finish,
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.system_off = tegra_system_off,
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.system_reset = tegra_system_reset,
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.validate_power_state = tegra_validate_power_state,
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.get_sys_suspend_power_state = tegra_get_sys_suspend_power_state
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};
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/*******************************************************************************
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* Export the platform specific power ops & initialize the fvp power controller
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******************************************************************************/
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int platform_setup_pm(const plat_pm_ops_t **plat_ops)
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{
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/*
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* Reset hardware settings.
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*/
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tegra_soc_prepare_cpu_on_finish(read_mpidr());
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/*
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* Initialize PM ops struct
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*/
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*plat_ops = &tegra_plat_pm_ops;
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return 0;
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}
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