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e234ba038b
The communication protocol used between the AP cores and the SCP
in CSS-based platforms like Juno has undergone a number of changes.
This patch makes the required modifications to the SCP Boot Protocol,
SCPI Protocol and MHU driver code in shared CSS platform code so that
the AP cores are still able to communicate with the SCP.
This patch focuses on the mandatory changes to make it work. The
design of this code needs to be improved but this will come in
a subsequent patch.
The main changes are:
- MHU communication protocol
- The command ID and payload size are no longer written into the
MHU registers directly. Instead, they are stored in the payload
area. The MHU registers are now used only as a doorbell to kick
off messages. Same goes for any command result, the AP has to
pick it up from the payload area.
- SCP Boot Protocol
- The BL3-0 image is now expected to embed a checksum. This
checksum must be passed to the SCP, which uses it to check the
integrity of the image it received.
- The BL3-0 image used to be transferred a block (4KB)
at a time. The SCP now supports receiving up to 128KB at a
time, which is more than the size of the BL3-0 image.
Therefore, the image is now sent in one go.
- The command IDs have changed.
- SCPI Protocol
- The size of the SCPI payload has been reduced down from 512
bytes to 256 bytes. This changes the base address of the
AP-to-SCP payload area.
- For commands that have a response, the response is the same SCPI
header that was sent, except for the size and the status, which
both must be updated appropriately. Success/Failure of a command
is determined by looking at the updated status code.
- Some command IDs have changed.
NOTE: THIS PATCH BREAKS COMPATIBILITY WITH FORMER VERSIONS OF THE SCP
FIRMWARE AND THUS REQUIRES AN UPDATE OF THIS BINARY. THE LATEST SCP
BINARY CAN BE OBTAINED FROM THE ARM CONNECTED COMMUNITY WEBSITE.
Change-Id: Ia5f6b95fe32401ee04a3805035748e8ef6718da7
120 lines
3.5 KiB
C
120 lines
3.5 KiB
C
/*
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* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bakery_lock.h>
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#include <css_def.h>
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#include <mmio.h>
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#include <plat_arm.h>
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#include "css_mhu.h"
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/* SCP MHU secure channel registers */
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#define SCP_INTR_S_STAT 0x200
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#define SCP_INTR_S_SET 0x208
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#define SCP_INTR_S_CLEAR 0x210
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/* CPU MHU secure channel registers */
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#define CPU_INTR_S_STAT 0x300
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#define CPU_INTR_S_SET 0x308
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#define CPU_INTR_S_CLEAR 0x310
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ARM_INSTANTIATE_LOCK
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/* Weak definition may be overridden in specific CSS based platform */
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#pragma weak plat_arm_pwrc_setup
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/*
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* Slot 31 is reserved because the MHU hardware uses this register bit to
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* indicate a non-secure access attempt. The total number of available slots is
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* therefore 31 [30:0].
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*/
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#define MHU_MAX_SLOT_ID 30
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void mhu_secure_message_start(unsigned int slot_id)
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{
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assert(slot_id <= MHU_MAX_SLOT_ID);
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arm_lock_get();
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/* Make sure any previous command has finished */
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while (mmio_read_32(MHU_BASE + CPU_INTR_S_STAT) & (1 << slot_id))
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;
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}
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void mhu_secure_message_send(unsigned int slot_id)
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{
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assert(slot_id <= MHU_MAX_SLOT_ID);
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assert(!(mmio_read_32(MHU_BASE + CPU_INTR_S_STAT) & (1 << slot_id)));
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/* Send command to SCP */
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mmio_write_32(MHU_BASE + CPU_INTR_S_SET, 1 << slot_id);
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}
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uint32_t mhu_secure_message_wait(void)
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{
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/* Wait for response from SCP */
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uint32_t response;
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while (!(response = mmio_read_32(MHU_BASE + SCP_INTR_S_STAT)))
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;
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return response;
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}
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void mhu_secure_message_end(unsigned int slot_id)
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{
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assert(slot_id <= MHU_MAX_SLOT_ID);
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/*
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* Clear any response we got by writing one in the relevant slot bit to
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* the CLEAR register
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*/
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mmio_write_32(MHU_BASE + SCP_INTR_S_CLEAR, 1 << slot_id);
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arm_lock_release();
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}
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void mhu_secure_init(void)
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{
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arm_lock_init();
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/*
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* The STAT register resets to zero. Ensure it is in the expected state,
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* as a stale or garbage value would make us think it's a message we've
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* already sent.
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*/
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assert(mmio_read_32(MHU_BASE + CPU_INTR_S_STAT) == 0);
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}
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void plat_arm_pwrc_setup(void)
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{
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mhu_secure_init();
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}
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