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https://github.com/ARM-software/arm-trusted-firmware.git
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95cfd4ad84
This patch extends the platform port by adding an API that returns
either the Root of Trust public key (ROTPK) or its hash. This is
usually stored in ROM or eFUSE memory. The ROTPK returned must be
encoded in DER format according to the following ASN.1 structure:
SubjectPublicKeyInfo ::= SEQUENCE {
algorithm AlgorithmIdentifier,
subjectPublicKey BIT STRING
}
In case the platform returns a hash of the key:
DigestInfo ::= SEQUENCE {
digestAlgorithm AlgorithmIdentifier,
keyDigest OCTET STRING
}
An implementation for ARM development platforms is provided in this
patch. When TBB is enabled, the ROTPK hash location must be specified
using the build option 'ARM_ROTPK_LOCATION'. Available options are:
- 'regs' : return the ROTPK hash stored in the Trusted
root-key storage registers.
- 'devel_rsa' : return a ROTPK hash embedded in the BL1 and
BL2 binaries. This hash has been obtained from the development
RSA public key located in 'plat/arm/board/common/rotpk'.
On FVP, the number of MMU tables has been increased to map and
access the ROTPK registers.
A new file 'board_common.mk' has been added to improve code sharing
in the ARM develelopment platforms.
Change-Id: Ib25862e5507d1438da10773e62bd338da8f360bf
145 lines
4.8 KiB
C
145 lines
4.8 KiB
C
/*
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* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __FVP_DEF_H__
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#define __FVP_DEF_H__
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#include <arm_def.h>
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#define FVP_MAX_CPUS_PER_CLUSTER 4
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#define FVP_PRIMARY_CPU 0x0
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/*******************************************************************************
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* FVP memory map related constants
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******************************************************************************/
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#define FLASH1_BASE 0x0c000000
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#define FLASH1_SIZE 0x04000000
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#define PSRAM_BASE 0x14000000
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#define PSRAM_SIZE 0x04000000
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#define VRAM_BASE 0x18000000
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#define VRAM_SIZE 0x02000000
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/* Aggregate of all devices in the first GB */
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#define DEVICE0_BASE 0x20000000
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#define DEVICE0_SIZE 0x0c200000
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#define DEVICE1_BASE 0x2f000000
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#define DEVICE1_SIZE 0x200000
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/* Devices in the second GB */
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#define DEVICE2_BASE 0x7fe00000
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#define DEVICE2_SIZE 0x00200000
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#define NSRAM_BASE 0x2e000000
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#define NSRAM_SIZE 0x10000
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#define PCIE_EXP_BASE 0x40000000
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#define TZRNG_BASE 0x7fe60000
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#define TZNVCTR_BASE 0x7fe70000
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/* Keys */
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#define SOC_KEYS_BASE 0x7fe80000
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#define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000)
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#define TZ_PUB_KEY_HASH_SIZE 32
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#define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020)
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#define HU_KEY_SIZE 16
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#define END_KEY_BASE (SOC_KEYS_BASE + 0x0044)
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#define END_KEY_SIZE 32
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/* Constants to distinguish FVP type */
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#define HBI_BASE_FVP 0x020
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#define REV_BASE_FVP_V0 0x0
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#define HBI_FOUNDATION_FVP 0x010
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#define REV_FOUNDATION_FVP_V2_0 0x0
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#define REV_FOUNDATION_FVP_V2_1 0x1
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#define REV_FOUNDATION_FVP_v9_1 0x2
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#define BLD_GIC_VE_MMAP 0x0
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#define BLD_GIC_A53A57_MMAP 0x1
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#define ARCH_MODEL 0x1
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/* FVP Power controller base address*/
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#define PWRC_BASE 0x1c100000
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/* FVP SP804 timer frequency is 35 MHz*/
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#define SP804_TIMER_CLKMULT 35
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#define SP804_TIMER_CLKDIV 1
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/*******************************************************************************
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* GIC-400 & interrupt handling related constants
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******************************************************************************/
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/* VE compatible GIC memory map */
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#define VE_GICD_BASE 0x2c001000
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#define VE_GICC_BASE 0x2c002000
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#define VE_GICH_BASE 0x2c004000
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#define VE_GICV_BASE 0x2c006000
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/* Base FVP compatible GIC memory map */
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#define BASE_GICD_BASE 0x2f000000
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#define BASE_GICR_BASE 0x2f100000
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#define BASE_GICC_BASE 0x2c000000
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#define BASE_GICH_BASE 0x2c010000
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#define BASE_GICV_BASE 0x2c02f000
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#define IRQ_TZ_WDOG 56
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/*******************************************************************************
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* TrustZone address space controller related constants
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******************************************************************************/
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/* NSAIDs used by devices in TZC filter 0 on FVP */
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#define FVP_NSAID_DEFAULT 0
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#define FVP_NSAID_PCI 1
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#define FVP_NSAID_VIRTIO 8 /* from FVP v5.6 onwards */
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#define FVP_NSAID_AP 9 /* Application Processors */
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#define FVP_NSAID_VIRTIO_OLD 15 /* until FVP v5.5 */
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/* NSAIDs used by devices in TZC filter 2 on FVP */
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#define FVP_NSAID_HDLCD0 2
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#define FVP_NSAID_CLCD 7
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/*******************************************************************************
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* Shared Data
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******************************************************************************/
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/* Entrypoint mailboxes */
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#define MBOX_BASE ARM_SHARED_RAM_BASE
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#define MBOX_SIZE 0x200
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#endif /* __FVP_DEF_H__ */
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