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https://github.com/ARM-software/arm-trusted-firmware.git
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96eaafa3f8
Make PMC IPI channel for Versal as secure so that NS systems cannot directly access or modify secure systems. Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Change-Id: I22148653fa2d27941cb3031ac790892cee0d1796
77 lines
1.6 KiB
C
77 lines
1.6 KiB
C
/*
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* Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
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* Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* Versal IPI agent registers access management
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*/
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#include <lib/utils_def.h>
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#include <ipi.h>
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#include <plat_ipi.h>
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/* versal ipi configuration table */
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static const struct ipi_config versal_ipi_table[] = {
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/* PMC IPI */
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[IPI_ID_PMC] = {
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.ipi_bit_mask = PMC_IPI_TRIG_BIT,
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.ipi_reg_base = PMC_REG_BASE,
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.secure_only = IPI_SECURE_MASK,
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},
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/* A72 IPI */
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[IPI_ID_APU] = {
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.ipi_bit_mask = IPI0_TRIG_BIT,
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.ipi_reg_base = IPI0_REG_BASE,
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.secure_only = 0U,
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},
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/* RPU0 IPI */
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[IPI_ID_RPU0] = {
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.ipi_bit_mask = IPI1_TRIG_BIT,
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.ipi_reg_base = IPI1_REG_BASE,
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.secure_only = 0U,
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},
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/* RPU1 IPI */
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[IPI_ID_RPU1] = {
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.ipi_bit_mask = IPI2_TRIG_BIT,
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.ipi_reg_base = IPI2_REG_BASE,
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.secure_only = 0U,
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},
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/* IPI3 IPI */
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[IPI_ID_3] = {
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.ipi_bit_mask = IPI3_TRIG_BIT,
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.ipi_reg_base = IPI3_REG_BASE,
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.secure_only = 0U,
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},
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/* IPI4 IPI */
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[IPI_ID_4] = {
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.ipi_bit_mask = IPI4_TRIG_BIT,
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.ipi_reg_base = IPI4_REG_BASE,
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.secure_only = 0U,
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},
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/* IPI5 IPI */
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[IPI_ID_5] = {
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.ipi_bit_mask = IPI5_TRIG_BIT,
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.ipi_reg_base = IPI5_REG_BASE,
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.secure_only = 0U,
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},
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};
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/* versal_ipi_config_table_init() - Initialize versal IPI configuration data.
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* @ipi_config_table: IPI configuration table.
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* @ipi_total: Total number of IPI available.
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*
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*/
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void versal_ipi_config_table_init(void)
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{
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ipi_config_table_init(versal_ipi_table, ARRAY_SIZE(versal_ipi_table));
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}
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