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https://github.com/ARM-software/arm-trusted-firmware.git
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3007c72844
When STM32MP2 boots on Cortex-M33, the Cortex-A35 do no more have access to BSEC peripheral. New static inline stm32_otp_* wrappers are added, which just redirect to BSEC functions. While at it remove a useless bsec.h include. Change-Id: Ie0f917c02e48acf456634f455dae41805bf6adbf Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
62 lines
1.5 KiB
C
62 lines
1.5 KiB
C
/*
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* Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef STM32MP1_PRIVATE_H
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#define STM32MP1_PRIVATE_H
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#include <stdint.h>
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void configure_mmu(void);
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void stm32mp1_arch_security_setup(void);
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void stm32mp1_security_setup(void);
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void stm32mp1_syscfg_init(void);
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void stm32mp1_syscfg_enable_io_compensation_start(void);
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void stm32mp1_syscfg_enable_io_compensation_finish(void);
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void stm32mp1_syscfg_disable_io_compensation(void);
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uint32_t stm32mp1_syscfg_get_chip_version(void);
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uint32_t stm32mp1_syscfg_get_chip_dev_id(void);
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#if STM32MP13
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void stm32mp1_syscfg_boot_mode_enable(void);
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void stm32mp1_syscfg_boot_mode_disable(void);
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#endif
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#if STM32MP15
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static inline void stm32mp1_syscfg_boot_mode_enable(void){}
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static inline void stm32mp1_syscfg_boot_mode_disable(void){}
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#endif
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void stm32mp1_deconfigure_uart_pins(void);
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void stm32mp1_init_scmi_server(void);
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/* Wrappers for OTP / BSEC functions */
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static inline uint32_t stm32_otp_read(uint32_t *val, uint32_t otp)
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{
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return bsec_read_otp(val, otp);
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}
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static inline uint32_t stm32_otp_shadow_read(uint32_t *val, uint32_t otp)
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{
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return bsec_shadow_read_otp(val, otp);
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}
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static inline uint32_t stm32_otp_write(uint32_t val, uint32_t otp)
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{
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return bsec_write_otp(val, otp);
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}
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static inline uint32_t stm32_otp_set_sr_lock(uint32_t otp)
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{
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return bsec_set_sr_lock(otp);
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}
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static inline uint32_t stm32_otp_read_sw_lock(uint32_t otp, bool *value)
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{
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return bsec_read_sw_lock(otp, value);
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}
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#endif /* STM32MP1_PRIVATE_H */
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