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6744d07d94
RPi 5 has newer Armv8.2 cores where the MT bit is set to indicate that the lowest affinity level represents a thread, but there is only one thread per core. To deal with this, simply right shift MPIDR by one affinity level to get the cluster and core IDs back into Aff1 and Aff0 as expected. Change-Id: I2bafba38f82fd9a6ef6f2fdf2c089b754279a6de Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
73 lines
2 KiB
C
73 lines
2 KiB
C
/*
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* Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdint.h>
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#include <platform_def.h>
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#include <arch.h>
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#include <rpi_shared.h>
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/* The power domain tree descriptor */
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static unsigned char power_domain_tree_desc[] = {
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/* Number of root nodes */
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PLATFORM_CLUSTER_COUNT,
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/* Number of children for the first node */
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PLATFORM_CLUSTER0_CORE_COUNT,
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};
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/*******************************************************************************
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* This function returns the ARM default topology tree information.
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******************************************************************************/
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const unsigned char *plat_get_power_domain_tree_desc(void)
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{
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return power_domain_tree_desc;
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}
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/*******************************************************************************
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* This function implements a part of the critical interface between the psci
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* generic layer and the platform that allows the former to query the platform
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* to convert an MPIDR to a unique linear index. An error code (-1) is returned
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* in case the MPIDR is invalid.
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******************************************************************************/
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int plat_core_pos_by_mpidr(u_register_t mpidr)
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{
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unsigned int cluster_id, cpu_id;
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mpidr &= MPIDR_AFFINITY_MASK;
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/*
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* When MT is set, lowest affinity represents the thread ID.
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* Since we only support one thread per core, discard this field
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* so cluster and core IDs go back into Aff1 and Aff0 respectively.
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* The upper bits are also affected, but plat_rpi3_calc_core_pos()
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* does not use them.
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*/
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if ((read_mpidr() & MPIDR_MT_MASK) != 0) {
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if (MPIDR_AFFLVL0_VAL(mpidr) != 0) {
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return -1;
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}
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mpidr >>= MPIDR_AFFINITY_BITS;
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}
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if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) {
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return -1;
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}
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cluster_id = MPIDR_AFFLVL1_VAL(mpidr);
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cpu_id = MPIDR_AFFLVL0_VAL(mpidr);
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if (cluster_id >= PLATFORM_CLUSTER_COUNT) {
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return -1;
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}
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if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) {
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return -1;
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}
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return plat_rpi3_calc_core_pos(mpidr);
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}
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