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1e67b1b17a
QEMU provides GIC information in DeviceTree (on platform version 0.1+). Read it and provide to next firmware level via SMC. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Change-Id: I383919bd172acc8873292a0c5e4469651dc96fb9
67 lines
1.6 KiB
C
67 lines
1.6 KiB
C
/*
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* Copyright (c) 2023, Linaro Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <drivers/arm/gicv3.h>
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#include <plat/common/platform.h>
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static const interrupt_prop_t qemu_interrupt_props[] = {
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PLATFORM_G1S_PROPS(INTR_GROUP1S),
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PLATFORM_G0_PROPS(INTR_GROUP0)
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};
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static uintptr_t qemu_rdistif_base_addrs[PLATFORM_CORE_COUNT];
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static unsigned int qemu_mpidr_to_core_pos(unsigned long mpidr)
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{
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return plat_core_pos_by_mpidr(mpidr);
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}
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static gicv3_driver_data_t sbsa_gic_driver_data = {
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/* we set those two values for compatibility with older QEMU */
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.gicd_base = GICD_BASE,
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.gicr_base = GICR_BASE,
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.interrupt_props = qemu_interrupt_props,
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.interrupt_props_num = ARRAY_SIZE(qemu_interrupt_props),
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.rdistif_num = PLATFORM_CORE_COUNT,
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.rdistif_base_addrs = qemu_rdistif_base_addrs,
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.mpidr_to_core_pos = qemu_mpidr_to_core_pos
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};
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void sbsa_set_gic_bases(const uintptr_t gicd_base, const uintptr_t gicr_base)
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{
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sbsa_gic_driver_data.gicd_base = gicd_base;
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sbsa_gic_driver_data.gicr_base = gicr_base;
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}
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uintptr_t sbsa_get_gicd(void)
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{
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return sbsa_gic_driver_data.gicd_base;
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}
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uintptr_t sbsa_get_gicr(void)
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{
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return sbsa_gic_driver_data.gicr_base;
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}
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void plat_qemu_gic_init(void)
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{
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gicv3_driver_init(&sbsa_gic_driver_data);
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gicv3_distif_init();
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gicv3_rdistif_init(plat_my_core_pos());
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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void qemu_pwr_gic_on_finish(void)
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{
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gicv3_rdistif_init(plat_my_core_pos());
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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void qemu_pwr_gic_off(void)
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{
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gicv3_cpuif_disable(plat_my_core_pos());
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gicv3_rdistif_off(plat_my_core_pos());
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}
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