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https://github.com/ARM-software/arm-trusted-firmware.git
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e8faff3da9
Fix OCRAM ECC for lx2 platform. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: Ic46de7a40c611764a6f24400663da50e6b477ae5
119 lines
3 KiB
Modula-2
119 lines
3 KiB
Modula-2
#
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# Copyright (c) 2015, 2016 Freescale Semiconductor, Inc.
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# Copyright 2017-2022 NXP Semiconductors
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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#
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#------------------------------------------------------------------------------
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#
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# This file contains the basic architecture definitions that drive the build
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#
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# -----------------------------------------------------------------------------
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CORE_TYPE := a72
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CACHE_LINE := 6
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# set to GIC400 or GIC500
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GIC := GIC500
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# set to CCI400 or CCN504 or CCN508
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INTERCONNECT := CCN508
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# indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2
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CHASSIS := 3_2
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# TZC IP Details TZC used is TZC380 or TZC400
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TZC_ID := TZC400
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# CONSOLE Details available is NS16550 or PL011
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CONSOLE := PL011
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# Select the DDR PHY generation to be used
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PLAT_DDR_PHY := PHY_GEN2
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PHYS_SYS := 64
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# Area of OCRAM reserved by ROM code
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NXP_ROM_RSVD := 0xa000
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# Max Size of CSF header. Required to define BL2 TEXT LIMIT in soc.def
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# Input to CST create_hdr_esbc tool
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CSF_HDR_SZ := 0x3000
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NXP_SFP_VER := 3_4
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# In IMAGE_BL2, compile time flag for handling Cache coherency
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# with CAAM for BL2 running from OCRAM
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SEC_MEM_NON_COHERENT := yes
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# Defining the endianness for NXP ESDHC
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NXP_ESDHC_ENDIANNESS := LE
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# Defining the endianness for NXP SFP
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NXP_SFP_ENDIANNESS := LE
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# Defining the endianness for NXP GPIO
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NXP_GPIO_ENDIANNESS := LE
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# Defining the endianness for NXP SNVS
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NXP_SNVS_ENDIANNESS := LE
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# Defining the endianness for NXP CCSR GUR register
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NXP_GUR_ENDIANNESS := LE
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# Defining the endianness for NXP FSPI register
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NXP_FSPI_ENDIANNESS := LE
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# Defining the endianness for NXP SEC
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NXP_SEC_ENDIANNESS := LE
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# Defining the endianness for NXP DDR
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NXP_DDR_ENDIANNESS := LE
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NXP_DDR_INTLV_256B := 1
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# OCRAM MAP for BL2
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# Before BL2
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# 0x18000000 - 0x18009fff -> Used by ROM code
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# 0x1800a000 - 0x1800dfff -> CSF header for BL2
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# (The above area i.e 0x18000000 - 0x1800dfff is available
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# for DDR PHY images scratch pad region during BL2 run time)
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# For FlexSPI boot
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# 0x1800e000 - 0x18040000 -> Reserved for BL2 binary
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# For SD boot
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# 0x1800e000 - 0x18030000 -> Reserved for BL2 binary
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# 0x18030000 - 0x18040000 -> Reserved for SD buffer
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OCRAM_START_ADDR := 0x18000000
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OCRAM_SIZE := 0x40000
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# Location of BL2 on OCRAM
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BL2_BASE_ADDR := $(shell echo $$(( $(OCRAM_START_ADDR) + $(NXP_ROM_RSVD) + $(CSF_HDR_SZ) )))
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# Covert to HEX to be used by create_pbl.mk
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BL2_BASE := $(shell echo "0x"$$(echo "obase=16; ${BL2_BASE_ADDR}" | bc))
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# BL2_HDR_LOC is at (OCRAM_ADDR + NXP_ROM_RSVD)
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# This value BL2_HDR_LOC + CSF_HDR_SZ should not overalp with BL2_BASE
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BL2_HDR_LOC_HDR ?= $(shell echo $$(( $(OCRAM_START_ADDR) + $(NXP_ROM_RSVD) )))
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# Covert to HEX to be used by create_pbl.mk
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BL2_HDR_LOC := $$(echo "obase=16; ${BL2_HDR_LOC_HDR}" | bc)
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# SoC ERRATAS to be enabled
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#
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# Core Errata
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ERRATA_A72_859971 := 1
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# SoC Errata
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ERRATA_SOC_A050426 := 1
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# DDR Errata
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ERRATA_DDR_A011396 := 1
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ERRATA_DDR_A050450 := 1
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ERRATA_DDR_A050958 := 1
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# enable dynamic memory mapping
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PLAT_XLAT_TABLES_DYNAMIC := 1
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# OCRAM ECC Enabled
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OCRAM_ECC_EN := yes
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