mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-24 13:55:56 +00:00
c0c157a680
Changed the size of OCRAM reserved by ROM code and increased the size of CSF header. Earlier, 4 keys image was exceeding boundaries and landing in OCRAM location reserved for ROM usage. Signed-off by:- Kshitiz Varshney <kshitiz.varshney@nxp.com> Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I628ff7464fe0184d0553a7962d592aafd42e8137
107 lines
2.6 KiB
Modula-2
107 lines
2.6 KiB
Modula-2
#
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# Copyright 2022 NXP
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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#
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#------------------------------------------------------------------------------
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#
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# This file contains the basic architecture definitions that drive the build
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#
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# -----------------------------------------------------------------------------
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CORE_TYPE := a72
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CACHE_LINE := 6
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# set to GIC400 or GIC500
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GIC := GIC400
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# set to CCI400 or CCN504 or CCN508
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INTERCONNECT := CCI400
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# indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2
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CHASSIS := 2
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# TZC IP Details TZC used is TZC380 or TZC400
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TZC_ID := TZC400
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# CONSOLE Details available is NS16550 or PL011
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CONSOLE := NS16550
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# Select the DDR PHY generation to be used
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PLAT_DDR_PHY := PHY_GEN1
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PHYS_SYS := 64
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# ddr controller - set to MMDC or NXP
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DDRCNTLR := NXP
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# ddr phy - set to NXP or SNPS
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DDRPHY := NXP
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# Area of OCRAM reserved by ROM code
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NXP_ROM_RSVD := 0x8000
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# Max Size of CSF header. Required to define BL2 TEXT LIMIT in soc.def
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# Input to CST create_hdr_esbc tool
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CSF_HDR_SZ := 0x4000
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# In IMAGE_BL2, compile time flag for handling Cache coherency
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# with CAAM for BL2 running from OCRAM
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SEC_MEM_NON_COHERENT := yes
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# OCRAM MAP
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OCRAM_START_ADDR := 0x10000000
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OCRAM_SIZE := 0x20000
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# BL2 binary is placed at start of OCRAM.
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# Also used by create_pbl.mk.
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BL2_BASE := 0x10000000
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# After BL2 bin, OCRAM is used by ROM Code:
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# (OCRAM_START_ADDR + BL2_BIN_SIZE) -> (NXP_ROM_RSVD - 1)
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# After ROM Code, OCRAM is used by CSF header.
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# (OCRAM_START_ADDR + BL2_TEXT_LIMIT + NXP_ROM_RSVD) -> (CSF_HDR_SZ - 1)
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# BL2_HDR_LOC has to be (OCRAM_START_ADDR + OCRAM_SIZE - NXP_ROM_RSVD - CSF_HDR_SZ)
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# This value should be greater than BL2_TEXT_LIMIT
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# Input to CST create_hdr_isbc tool
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BL2_HDR_LOC_HDR ?= $(shell echo $$(( $(OCRAM_START_ADDR) + $(OCRAM_SIZE) - $(NXP_ROM_RSVD) - $(CSF_HDR_SZ))))
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# Covert to HEX to be used by create_pbl.mk
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BL2_HDR_LOC := $$(echo "obase=16; ${BL2_HDR_LOC_HDR}" | bc)
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# Core Errata
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ERRATA_A72_859971 := 1
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# SoC ERRATAS
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ERRATA_SOC_A008850 := 1
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ERRATA_SOC_A010539 := 1
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# DDR Errata
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ERRATA_DDR_A008511 := 1
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ERRATA_DDR_A009803 := 1
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ERRATA_DDR_A009942 := 1
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ERRATA_DDR_A010165 := 1
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# enable dynamic memory mapping
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PLAT_XLAT_TABLES_DYNAMIC := 1
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# Define Endianness of each module
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NXP_GUR_ENDIANNESS := BE
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NXP_DDR_ENDIANNESS := BE
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NXP_SEC_ENDIANNESS := BE
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NXP_SFP_ENDIANNESS := BE
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NXP_SNVS_ENDIANNESS := BE
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NXP_ESDHC_ENDIANNESS := BE
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NXP_QSPI_ENDIANNESS := BE
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NXP_FSPI_ENDIANNESS := BE
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NXP_SCFG_ENDIANNESS := BE
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NXP_GPIO_ENDIANNESS := BE
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NXP_IFC_ENDIANNESS := BE
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NXP_SFP_VER := 3_2
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# OCRAM ECC Enabled
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OCRAM_ECC_EN := yes
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