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https://github.com/ARM-software/arm-trusted-firmware.git
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b51dc56ab9
The LS1046A Freeway board (FRWY) is a high-performance computing, evaluation, and development platform that supports the LS1046A architecture processor capable of support more than 32,000 CoreMark performance. The FRWY-LS1046A board supports the LS1046A processor, onboard DDR4 memory, multiple Gigabit Ethernet, USB3.0 and M2_Type_E interfaces for Wi-Fi, FRWY-LS1046A-AC includes the Wi-Fi card. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I9a9680689e6f17bf4cc76fd5d1883eed6ace5149
177 lines
4 KiB
C
177 lines
4 KiB
C
/*
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* Copyright 2018-2022 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <string.h>
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#include <common/debug.h>
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#include <ddr.h>
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#include <lib/utils.h>
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#include <errata.h>
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#include <platform_def.h>
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#ifdef CONFIG_STATIC_DDR
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const struct ddr_cfg_regs static_1600 = {
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.cs[0].config = U(0x80010412),
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.cs[0].bnds = U(0x7F),
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.sdram_cfg[0] = U(0xE50C0008),
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.sdram_cfg[1] = U(0x00401010),
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.sdram_cfg[2] = U(0x1),
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.timing_cfg[0] = U(0xFA550018),
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.timing_cfg[1] = U(0xBAB40C52),
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.timing_cfg[2] = U(0x0048C11C),
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.timing_cfg[3] = U(0x01111000),
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.timing_cfg[4] = U(0x00000002),
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.timing_cfg[5] = U(0x03401400),
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.timing_cfg[6] = U(0x0),
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.timing_cfg[7] = U(0x23300000),
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.timing_cfg[8] = U(0x02116600),
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.timing_cfg[9] = U(0x0),
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.dq_map[0] = U(0x0),
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.dq_map[1] = U(0x0),
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.dq_map[2] = U(0x0),
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.dq_map[3] = U(0x0),
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.sdram_mode[0] = U(0x01010210),
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.sdram_mode[1] = U(0x0),
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.sdram_mode[8] = U(0x00000500),
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.sdram_mode[9] = U(0x04000000),
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.interval = U(0x18600618),
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.zq_cntl = U(0x8A090705),
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.ddr_sr_cntr = U(0x0),
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.clk_cntl = U(0x2000000),
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.cdr[0] = U(0x80040000),
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.cdr[1] = U(0xC1),
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.wrlvl_cntl[0] = U(0x86550607),
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.wrlvl_cntl[1] = U(0x07070708),
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.wrlvl_cntl[2] = U(0x0808088),
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};
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long long board_static_ddr(struct ddr_info *priv)
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{
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memcpy(&priv->ddr_reg, &static_1600, sizeof(static_1600));
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return 0x80000000ULL;
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}
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#else /* ifndef CONFIG_STATIC_DDR */
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static const struct rc_timing rcz[] = {
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{U(1600), U(8), U(7)},
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{U(2100), U(8), U(7)},
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{}
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};
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static const struct board_timing ram[] = {
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{U(0x1f), rcz, U(0x01010101), U(0x01010101)},
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};
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int ddr_board_options(struct ddr_info *priv)
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{
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int ret;
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struct memctl_opt *popts = &priv->opt;
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ret = cal_board_params(priv, ram, ARRAY_SIZE(ram));
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if (ret != 0) {
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return ret;
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}
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popts->bstopre = 0;
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popts->half_strength_drive_en = 1;
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popts->cpo_sample = U(0x46);
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popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_50ohm);
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popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_50ohm) |
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DDR_CDR2_VREF_TRAIN_EN;
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popts->output_driver_impedance = 1;
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return 0;
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}
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/* DDR model number: MT40A512M16JY-083E:B */
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struct dimm_params ddr_raw_timing = {
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.n_ranks = U(1),
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.rank_density = ULL(4294967296),
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.capacity = ULL(4294967296),
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.primary_sdram_width = U(64),
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.ec_sdram_width = U(8),
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.rdimm = U(0),
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.mirrored_dimm = U(0),
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.n_row_addr = U(16),
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.n_col_addr = U(10),
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.bank_group_bits = U(1),
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.edc_config = U(2),
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.burst_lengths_bitmask = U(0x0c),
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.tckmin_x_ps = 750,
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.tckmax_ps = 1900,
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.caslat_x = U(0x0001FFE00),
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.taa_ps = 13500,
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.trcd_ps = 13500,
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.trp_ps = 13500,
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.tras_ps = 33000,
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.trc_ps = 46500,
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.twr_ps = 15000,
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.trfc1_ps = 350000,
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.trfc2_ps = 260000,
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.trfc4_ps = 160000,
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.tfaw_ps = 30000,
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.trrds_ps = 5300,
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.trrdl_ps = 6400,
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.tccdl_ps = 5355,
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.refresh_rate_ps = U(7800000),
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.dq_mapping[0] = U(0x0),
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.dq_mapping[1] = U(0x0),
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.dq_mapping[2] = U(0x0),
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.dq_mapping[3] = U(0x0),
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.dq_mapping[4] = U(0x0),
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.dq_mapping_ors = U(0),
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.rc = U(0x1f),
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};
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int ddr_get_ddr_params(struct dimm_params *pdimm, struct ddr_conf *conf)
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{
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static const char dimm_model[] = "Fixed DDR on board";
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conf->dimm_in_use[0] = 1;
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memcpy(pdimm, &ddr_raw_timing, sizeof(struct dimm_params));
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memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
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return 1;
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}
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#endif /* ifdef CONFIG_STATIC_DDR */
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long long init_ddr(void)
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{
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int spd_addr[] = {NXP_SPD_EEPROM0};
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struct ddr_info info;
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struct sysinfo sys;
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long long dram_size;
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zeromem(&sys, sizeof(sys));
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if (get_clocks(&sys)) {
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ERROR("System clocks are not set\n");
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assert(0);
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}
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debug("platform clock %lu\n", sys.freq_platform);
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debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0);
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debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1);
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zeromem(&info, sizeof(struct ddr_info));
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info.num_ctlrs = 1;
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info.dimm_on_ctlr = 1;
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info.clk = get_ddr_freq(&sys, 0);
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info.spd_addr = spd_addr;
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info.ddr[0] = (void *)NXP_DDR_ADDR;
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dram_size = dram_init(&info);
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if (dram_size < 0) {
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ERROR("DDR init failed.\n");
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}
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#ifdef ERRATA_SOC_A008850
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erratum_a008850_post();
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#endif
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return dram_size;
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}
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