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https://github.com/ARM-software/arm-trusted-firmware.git
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3b0de91825
The LS1043A processor was NXP's first quad-core, 64-bit Arm based processor for embedded networking. The old implementation in tf-a (plat/layerscape/board/ls1043/) is removed, and this patch is adding it back, it is using the unified software component and architecture with all the other Layerscape platforms. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: rocket <rod.dorris@nxp.com> Change-Id: Ia3877530fae6479bd4a33bbe46b0c0d28ab43160
234 lines
7.6 KiB
C
234 lines
7.6 KiB
C
/*
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* Copyright 2017-2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOC_H
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#define SOC_H
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/* Chassis specific defines - common across SoC's of a particular platform */
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#include "dcfg_lsch2.h"
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#include "soc_default_base_addr.h"
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#include "soc_default_helper_macros.h"
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/* DDR Regions Info */
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#define NUM_DRAM_REGIONS 3
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#define NXP_DRAM0_ADDR 0x80000000
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#define NXP_DRAM0_MAX_SIZE 0x80000000 /* 2 GB */
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#define NXP_DRAM1_ADDR 0x880000000
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#define NXP_DRAM1_MAX_SIZE 0x780000000 /* 30 GB */
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#define NXP_DRAM2_ADDR 0x8800000000
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#define NXP_DRAM2_MAX_SIZE 0x7800000000 /* 480 GB */
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/* DRAM0 Size defined in platform_def.h */
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#define NXP_DRAM0_SIZE PLAT_DEF_DRAM0_SIZE
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/*
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* P23: 23 x 23 package
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* A: without security
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* AE: with security
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* SVR Definition (not include major and minor rev)
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*/
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#define SVR_LS1023A 0x879209
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#define SVR_LS1023AE 0x879208
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#define SVR_LS1023A_P23 0x87920B
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#define SVR_LS1023AE_P23 0x87920A
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#define SVR_LS1043A 0x879201
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#define SVR_LS1043AE 0x879200
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#define SVR_LS1043A_P23 0x879203
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#define SVR_LS1043AE_P23 0x879202
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/* Number of cores in platform */
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#define PLATFORM_CORE_COUNT 4
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#define NUMBER_OF_CLUSTERS 1
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#define CORES_PER_CLUSTER 4
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/* set to 0 if the clusters are not symmetrical */
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#define SYMMETRICAL_CLUSTERS 1
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/*
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* Required LS standard platform porting definitions
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* for CCI-400
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*/
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#define NXP_CCI_CLUSTER0_SL_IFACE_IX 4
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/* ls1043 version info for GIC configuration */
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#define REV1_0 0x10
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#define REV1_1 0x11
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#define GIC_ADDR_BIT 31
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/* Errata */
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#define NXP_ERRATUM_A009663
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#define NXP_ERRATUM_A009942
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#define NUM_OF_DDRC 1
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/* Defines required for using XLAT tables from ARM common code */
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 40)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 40)
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/* Clock Divisors */
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#define NXP_PLATFORM_CLK_DIVIDER 1
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#define NXP_UART_CLK_DIVIDER 1
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/*
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* Set this switch to 1 if you need to keep the debug block
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* clocked during system power-down.
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*/
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#define DEBUG_ACTIVE 0
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#define IPPDEXPCR_MAC1_1 0x80000000 // DEVDISR2_FMAN1_MAC1
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#define IPPDEXPCR_MAC1_2 0x40000000 // DEVDISR2_FMAN1_MAC2
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#define IPPDEXPCR_MAC1_3 0x20000000 // DEVDISR2_FMAN1_MAC3
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#define IPPDEXPCR_MAC1_4 0x10000000 // DEVDISR2_FMAN1_MAC4
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#define IPPDEXPCR_MAC1_5 0x08000000 // DEVDISR2_FMAN1_MAC5
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#define IPPDEXPCR_MAC1_6 0x04000000 // DEVDISR2_FMAN1_MAC6
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#define IPPDEXPCR_MAC1_9 0x00800000 // DEVDISR2_FMAN1_MAC9
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#define IPPDEXPCR_I2C1 0x00080000 // DEVDISR5_I2C_1
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#define IPPDEXPCR_LPUART1 0x00040000 // DEVDISR5_LPUART1
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#define IPPDEXPCR_FLX_TMR1 0x00020000 // DEVDISR5_FLX_TMR
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#define IPPDEXPCR_OCRAM1 0x00010000 // DEVDISR5_OCRAM1
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#define IPPDEXPCR_GPIO1 0x00000040 // DEVDISR5_GPIO
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#define IPPDEXPCR_FM1 0x00000008 // DEVDISR2_FMAN1
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#define IPPDEXPCR_MASK1 0xFC800008 // overrides for DEVDISR2
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#define IPPDEXPCR_MASK2 0x000F0040 // overriddes for DEVDISR5
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#define IPSTPCR0_VALUE 0xA000C201
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#define IPSTPCR1_VALUE 0x00000080
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#define IPSTPCR2_VALUE 0x000C0000
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#define IPSTPCR3_VALUE 0x38000000
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#if (DEBUG_ACTIVE)
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#define IPSTPCR4_VALUE 0x10833BFC
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#else
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#define IPSTPCR4_VALUE 0x10A33BFC
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#endif
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#define DEVDISR1_QE 0x00000001
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#define DEVDISR1_SEC 0x00000200
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#define DEVDISR1_USB1 0x00004000
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#define DEVDISR1_SATA 0x00008000
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#define DEVDISR1_USB2 0x00010000
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#define DEVDISR1_USB3 0x00020000
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#define DEVDISR1_DMA2 0x00400000
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#define DEVDISR1_DMA1 0x00800000
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#define DEVDISR1_ESDHC 0x20000000
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#define DEVDISR1_PBL 0x80000000
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#define DEVDISR2_FMAN1 0x00000080
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#define DEVDISR2_FMAN1_MAC9 0x00800000
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#define DEVDISR2_FMAN1_MAC6 0x04000000
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#define DEVDISR2_FMAN1_MAC5 0x08000000
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#define DEVDISR2_FMAN1_MAC4 0x10000000
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#define DEVDISR2_FMAN1_MAC3 0x20000000
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#define DEVDISR2_FMAN1_MAC2 0x40000000
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#define DEVDISR2_FMAN1_MAC1 0x80000000
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#define DEVDISR3_BMAN 0x00040000
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#define DEVDISR3_QMAN 0x00080000
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#define DEVDISR3_PEX3 0x20000000
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#define DEVDISR3_PEX2 0x40000000
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#define DEVDISR3_PEX1 0x80000000
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#define DEVDISR4_QSPI 0x08000000
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#define DEVDISR4_DUART2 0x10000000
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#define DEVDISR4_DUART1 0x20000000
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#define DEVDISR5_ICMMU 0x00000001
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#define DEVDISR5_I2C_1 0x00000002
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#define DEVDISR5_I2C_2 0x00000004
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#define DEVDISR5_I2C_3 0x00000008
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#define DEVDISR5_I2C_4 0x00000010
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#define DEVDISR5_WDG_5 0x00000020
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#define DEVDISR5_WDG_4 0x00000040
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#define DEVDISR5_WDG_3 0x00000080
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#define DEVDISR5_DSPI1 0x00000100
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#define DEVDISR5_WDG_2 0x00000200
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#define DEVDISR5_FLX_TMR 0x00000400
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#define DEVDISR5_WDG_1 0x00000800
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#define DEVDISR5_LPUART6 0x00001000
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#define DEVDISR5_LPUART5 0x00002000
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#define DEVDISR5_LPUART3 0x00008000
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#define DEVDISR5_LPUART2 0x00010000
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#define DEVDISR5_LPUART1 0x00020000
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#define DEVDISR5_DBG 0x00200000
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#define DEVDISR5_GPIO 0x00400000
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#define DEVDISR5_IFC 0x00800000
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#define DEVDISR5_OCRAM2 0x01000000
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#define DEVDISR5_OCRAM1 0x02000000
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#define DEVDISR5_LPUART4 0x10000000
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#define DEVDISR5_DDR 0x80000000
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#define DEVDISR5_MEM 0x80000000
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#define DEVDISR1_VALUE 0xA0C3C201
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#define DEVDISR2_VALUE 0xCC0C0080
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#define DEVDISR3_VALUE 0xE00C0000
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#define DEVDISR4_VALUE 0x38000000
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#if (DEBUG_ACTIVE)
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#define DEVDISR5_VALUE 0x10833BFC
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#else
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#define DEVDISR5_VALUE 0x10A33BFC
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#endif
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/*
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* PWR mgmt features supported in the soc-specific code:
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* value == 0x0 the soc code does not support this feature
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* value != 0x0 the soc code supports this feature
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*/
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#define SOC_CORE_RELEASE 0x1
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#define SOC_CORE_RESTART 0x1
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#define SOC_CORE_OFF 0x1
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#define SOC_CORE_STANDBY 0x1
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#define SOC_CORE_PWR_DWN 0x1
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#define SOC_CLUSTER_STANDBY 0x1
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#define SOC_CLUSTER_PWR_DWN 0x1
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#define SOC_SYSTEM_STANDBY 0x1
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#define SOC_SYSTEM_PWR_DWN 0x1
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#define SOC_SYSTEM_OFF 0x1
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#define SOC_SYSTEM_RESET 0x1
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/* PSCI-specific defines */
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#define SYSTEM_PWR_DOMAINS 1
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
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NUMBER_OF_CLUSTERS + \
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SYSTEM_PWR_DOMAINS)
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/* Power state coordination occurs at the system level */
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#define PLAT_PD_COORD_LVL MPIDR_AFFLVL2
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#define PLAT_MAX_PWR_LVL PLAT_PD_COORD_LVL
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/* Local power state for power domains in Run state */
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#define LS_LOCAL_STATE_RUN PSCI_LOCAL_STATE_RUN
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/* define retention state */
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#define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1)
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#define LS_LOCAL_STATE_RET PLAT_MAX_RET_STATE
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/* define power-down state */
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#define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1)
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#define LS_LOCAL_STATE_OFF PLAT_MAX_OFF_STATE
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/*
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* Some data must be aligned on the biggest cache line size in the platform.
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* This is known only to the platform as it might have a combination of
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* integrated and external caches.
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* CACHE_WRITEBACK_GRANULE is defined in soc.def
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*/
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/* One cache line needed for bakery locks on ARM platforms */
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#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
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#ifndef __ASSEMBLER__
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/* CCI slave interfaces */
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static const int cci_map[] = {
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NXP_CCI_CLUSTER0_SL_IFACE_IX,
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};
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void soc_init_lowlevel(void);
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void soc_init_percpu(void);
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void _soc_set_start_addr(unsigned long addr);
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#endif
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#endif /* SOC_H */
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