Marek Vasut f1bb459c31 feat(imx8m): add 3600 MTps DDR PLL rate ... Add 3600 MTps DRAM and its 900 MHz PLL setting M=300 P=8 S=0 , so 24 MHz * 300 / 8 / 2^0 = 900 MHz ~ 3600 MTps (x4) . Signed-off-by: Marek Vasut <marex@denx.de> Change-Id: If2743827294efc0f981718f04b772cc462846195		2023-12-02 06:47:44 +01:00
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clock.c	feat(imx8m): add 3600 MTps DDR PLL rate	2023-12-02 06:47:44 +01:00
ddr4_dvfs.c	fix(imx8m): add ddr4 dvfs sw workaround for ERR050712	2023-02-28 14:27:28 +08:00
dram.c	feat(imx8mq): enable dram dvfs support on imx8mq	2023-03-01 10:18:03 +08:00
dram_retention.c	feat(imx8m): move the gpc reg & macro to a separate header file	2023-08-31 17:35:28 +02:00
lpddr4_dvfs.c	fix(imx8m): fix the dfiphymaster setting after dvfs	2023-02-27 11:23:44 +08:00