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https://github.com/ARM-software/arm-trusted-firmware.git
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a5a966b12d
populate_next_bl_params_config already configures the register values to be passed to BL33 and puts the HW_CONFIG address in r1. Therefore, we do not need to override r0 here and should instead use r1 in BL33. Change-Id: I00b425301957b5b0510416e1fa1f3599c0359bfc Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
164 lines
3.9 KiB
C
164 lines
3.9 KiB
C
/*
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* Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <libfdt.h>
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#include <tc_plat.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <drivers/arm/css/css_mhu_doorbell.h>
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#include <drivers/arm/css/scmi.h>
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#include <drivers/arm/sbsa.h>
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#include <lib/fconf/fconf.h>
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#include <lib/fconf/fconf_dyn_cfg_getter.h>
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#include <plat/arm/common/plat_arm.h>
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#include <plat/common/platform.h>
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#ifdef PLATFORM_TEST_TFM_TESTSUITE
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#include <psa/crypto_platform.h>
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#include <psa/crypto_types.h>
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#include <psa/crypto_values.h>
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#endif /* PLATFORM_TEST_TFM_TESTSUITE */
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#ifdef PLATFORM_TEST_TFM_TESTSUITE
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/*
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* We pretend using an external RNG (through MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG
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* mbedTLS config option) so we need to provide an implementation of
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* mbedtls_psa_external_get_random(). Provide a fake one, since we do not
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* actually use any of external RNG and this function is only needed during
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* the execution of TF-M testsuite during exporting the public part of the
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* delegated attestation key.
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*/
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psa_status_t mbedtls_psa_external_get_random(
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mbedtls_psa_external_random_context_t *context,
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uint8_t *output, size_t output_size,
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size_t *output_length)
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{
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for (size_t i = 0U; i < output_size; i++) {
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output[i] = (uint8_t)(read_cntpct_el0() & 0xFFU);
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}
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*output_length = output_size;
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return PSA_SUCCESS;
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}
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#endif /* PLATFORM_TEST_TFM_TESTSUITE */
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static scmi_channel_plat_info_t tc_scmi_plat_info[] = {
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{
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.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
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.db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0),
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.db_preserve_mask = 0xfffffffe,
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.db_modify_mask = 0x1,
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.ring_doorbell = &mhuv2_ring_doorbell,
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}
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};
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void bl31_platform_setup(void)
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{
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tc_bl31_common_platform_setup();
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}
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scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id)
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{
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return &tc_scmi_plat_info[channel_id];
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}
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
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/* Fill the properties struct with the info from the config dtb */
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fconf_populate("FW_CONFIG", arg1);
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}
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#ifdef PLATFORM_TESTS
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static __dead2 void tc_run_platform_tests(void)
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{
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int tests_failed;
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printf("\nStarting platform tests...\n");
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#ifdef PLATFORM_TEST_NV_COUNTERS
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tests_failed = nv_counter_test();
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#elif PLATFORM_TEST_ROTPK
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tests_failed = rotpk_test();
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#elif PLATFORM_TEST_TFM_TESTSUITE
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tests_failed = run_platform_tests();
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#endif
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printf("Platform tests %s.\n",
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(tests_failed != 0) ? "failed" : "succeeded");
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/* Suspend booting, no matter the tests outcome. */
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printf("Suspend booting...\n");
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plat_error_handler(-1);
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}
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#endif
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void tc_bl31_common_platform_setup(void)
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{
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arm_bl31_platform_setup();
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#ifdef PLATFORM_TESTS
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tc_run_platform_tests();
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#endif
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}
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const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
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{
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return css_scmi_override_pm_ops(ops);
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}
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void __init bl31_plat_arch_setup(void)
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{
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arm_bl31_plat_arch_setup();
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/* HW_CONFIG was also loaded by BL2 */
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const struct dyn_cfg_dtb_info_t *hw_config_info;
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hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID);
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assert(hw_config_info != NULL);
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fconf_populate("HW_CONFIG", hw_config_info->config_addr);
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}
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#if defined(SPD_spmd) && (SPMC_AT_EL3 == 0)
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void tc_bl31_plat_runtime_setup(void)
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{
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/* Start secure watchdog timer. */
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plat_arm_secure_wdt_start();
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arm_bl31_plat_runtime_setup();
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}
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void bl31_plat_runtime_setup(void)
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{
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tc_bl31_plat_runtime_setup();
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}
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/*
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* Platform handler for Group0 secure interrupt.
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*/
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int plat_spmd_handle_group0_interrupt(uint32_t intid)
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{
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/* Trusted Watchdog timer is the only source of Group0 interrupt now. */
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if (intid == SBSA_SECURE_WDOG_INTID) {
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/* Refresh the timer. */
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plat_arm_secure_wdt_refresh();
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return 0;
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}
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return -1;
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}
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#endif /*defined(SPD_spmd) && (SPMC_AT_EL3 == 0)*/
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