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f45c6d8623
The application cores of the FPGAs used in Arm Ltd. start execution at address 0x0. This is the location of some (emulated) ROM area (which can be written to by the uploading tool). Since the arm_fpga port is configured to run from DRAM, we load BL31 to the beginning of DRAM (mapped at 2GB). This requires some small trampoline code in the "ROM" to jump to the BL31 entry point. To avoid some extra magic binary, add a tiny assembly file with that trivial jump instruction to the tree, so this binary can be created alongside BL31. Change-Id: I9e4439fc0f093fa24dd49a8377c9edb030fbb477 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
24 lines
710 B
ArmAsm
24 lines
710 B
ArmAsm
/*
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* Copyright (c) 2020, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* The Arm Ltd. FPGA images start execution at address 0x0, which is
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* mapped at an (emulated) ROM image. The payload uploader can write to
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* this memory, but write access by the CPU cores is prohibited.
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*
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* Provide a simple trampoline to start BL31 execution at the actual
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* load address. We put the DTB address in x0, so any code in DRAM could
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* make use of that information (not yet used in BL31 right now).
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*/
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#include <asm_macros.S>
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#include <common/bl_common.ld.h>
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.text
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.global _start
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_start:
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mov_imm x1, BL31_BASE /* beginning of DRAM */
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mov_imm x0, FPGA_PRELOADED_DTB_BASE
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br x1
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