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https://github.com/ARM-software/arm-trusted-firmware.git
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d4572303ed
At the moment we specified the BL31 memory limits to 1MB; since we typically have gigabytes of DRAM, we can be quite generous. However the default parameters expect the devicetree binary at 0x80070000, so we should actually make sure we have no code or data beyond that point. Limit the ARM FPGA BL31 memory footprint to this available 7*64K region. We stay within the limit at the moment, with more than half of it reserved for stacks, so this could be downsized later should we run into problems. The PIE addresses stay as they are, since the default addresses do not apply there anywhere, and the build is broken anyway. Change-Id: I7768af1a93ff67096f4359fc5f5feb66464bafaa Signed-off-by: Andre Przywara <andre.przywara@arm.com>
88 lines
2.5 KiB
C
88 lines
2.5 KiB
C
/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arch.h>
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#include <plat/common/common_def.h>
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#include <platform_def.h>
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#include "../fpga_def.h"
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#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
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#define PLATFORM_LINKER_ARCH aarch64
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#define PLATFORM_STACK_SIZE UL(0x800)
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#define CACHE_WRITEBACK_SHIFT U(6)
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#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
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#define PLATFORM_CORE_COUNT \
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(FPGA_MAX_CLUSTER_COUNT * \
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FPGA_MAX_CPUS_PER_CLUSTER * \
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FPGA_MAX_PE_PER_CPU)
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#define PLAT_NUM_PWR_DOMAINS (FPGA_MAX_CLUSTER_COUNT + PLATFORM_CORE_COUNT + 1)
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#if !ENABLE_PIE
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#define BL31_BASE UL(0x80000000)
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#define BL31_LIMIT UL(0x80070000)
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#else
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#define BL31_BASE UL(0x0)
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#define BL31_LIMIT UL(0x01000000)
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#endif
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#define PLAT_SDEI_NORMAL_PRI 0x70
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#define ARM_IRQ_SEC_PHY_TIMER 29
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#define ARM_IRQ_SEC_SGI_0 8
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#define ARM_IRQ_SEC_SGI_1 9
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#define ARM_IRQ_SEC_SGI_2 10
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#define ARM_IRQ_SEC_SGI_3 11
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#define ARM_IRQ_SEC_SGI_4 12
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#define ARM_IRQ_SEC_SGI_5 13
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#define ARM_IRQ_SEC_SGI_6 14
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#define ARM_IRQ_SEC_SGI_7 15
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/*
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* Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3
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* terminology. On a GICv2 system or mode, the lists will be merged and treated
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* as Group 0 interrupts.
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*/
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#define PLATFORM_G1S_PROPS(grp) \
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INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \
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GIC_INTR_CFG_EDGE)
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#define PLATFORM_G0_PROPS(grp) \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \
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GIC_INTR_CFG_EDGE)
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#define PLAT_MAX_RET_STATE 1
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#define PLAT_MAX_OFF_STATE 2
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
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#define PLAT_FPGA_HOLD_ENTRY_SHIFT 3
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#define PLAT_FPGA_HOLD_STATE_WAIT 0
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#define PLAT_FPGA_HOLD_STATE_GO 1
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#endif
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