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https://github.com/ARM-software/arm-trusted-firmware.git
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a9203edae7
Check_vector_size checks if the size of the vector fits in the size reserved for it. This check creates problems in the Clang assembler. A new macro, end_vector_entry, is added and check_vector_size is deprecated. This new macro fills the current exception vector until the next exception vector. If the size of the current vector is bigger than 32 instructions then it gives an error. Change-Id: Ie8545cf1003a1e31656a1018dd6b4c28a4eaf671 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
586 lines
16 KiB
ArmAsm
586 lines
16 KiB
ArmAsm
/*
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* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <context.h>
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#include <cpu_data.h>
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#include <ea_handle.h>
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#include <interrupt_mgmt.h>
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#include <platform_def.h>
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#include <runtime_svc.h>
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#include <smccc.h>
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.globl runtime_exceptions
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.globl sync_exception_sp_el0
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.globl irq_sp_el0
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.globl fiq_sp_el0
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.globl serror_sp_el0
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.globl sync_exception_sp_elx
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.globl irq_sp_elx
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.globl fiq_sp_elx
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.globl serror_sp_elx
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.globl sync_exception_aarch64
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.globl irq_aarch64
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.globl fiq_aarch64
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.globl serror_aarch64
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.globl sync_exception_aarch32
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.globl irq_aarch32
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.globl fiq_aarch32
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.globl serror_aarch32
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/*
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* Macro that prepares entry to EL3 upon taking an exception.
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*
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* With RAS_EXTENSION, this macro synchronizes pending errors with an ESB
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* instruction. When an error is thus synchronized, the handling is
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* delegated to platform EA handler.
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*
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* Without RAS_EXTENSION, this macro just saves x30, and unmasks
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* Asynchronous External Aborts.
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*/
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.macro check_and_unmask_ea
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#if RAS_EXTENSION
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/* Synchronize pending External Aborts */
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esb
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/* Unmask the SError interrupt */
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msr daifclr, #DAIF_ABT_BIT
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/*
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* Explicitly save x30 so as to free up a register and to enable
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* branching
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*/
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str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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/* Check for SErrors synchronized by the ESB instruction */
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mrs x30, DISR_EL1
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tbz x30, #DISR_A_BIT, 1f
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/* Save GP registers and restore them afterwards */
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bl save_gp_registers
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mov x0, #ERROR_EA_ESB
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mrs x1, DISR_EL1
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bl delegate_ea
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bl restore_gp_registers
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1:
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#else
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/* Unmask the SError interrupt */
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msr daifclr, #DAIF_ABT_BIT
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str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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#endif
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.endm
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/*
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* Handle External Abort by delegating to the platform's EA handler.
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* Once the platform handler returns, the macro exits EL3 and returns to
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* where the abort was taken from.
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*
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* This macro assumes that x30 is available for use.
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*
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* 'abort_type' is a constant passed to the platform handler, indicating
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* the cause of the External Abort.
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*/
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.macro handle_ea abort_type
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/* Save GP registers */
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bl save_gp_registers
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/* Setup exception class and syndrome arguments for platform handler */
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mov x0, \abort_type
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mrs x1, esr_el3
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adr x30, el3_exit
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b delegate_ea
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.endm
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/* ---------------------------------------------------------------------
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* This macro handles Synchronous exceptions.
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* Only SMC exceptions are supported.
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* ---------------------------------------------------------------------
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*/
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.macro handle_sync_exception
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#if ENABLE_RUNTIME_INSTRUMENTATION
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/*
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* Read the timestamp value and store it in per-cpu data. The value
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* will be extracted from per-cpu data by the C level SMC handler and
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* saved to the PMF timestamp region.
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*/
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mrs x30, cntpct_el0
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str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
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mrs x29, tpidr_el3
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str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET]
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ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
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#endif
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mrs x30, esr_el3
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ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
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/* Handle SMC exceptions separately from other synchronous exceptions */
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cmp x30, #EC_AARCH32_SMC
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b.eq smc_handler32
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cmp x30, #EC_AARCH64_SMC
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b.eq smc_handler64
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/* Check for I/D aborts from lower EL */
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cmp x30, #EC_IABORT_LOWER_EL
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b.eq 1f
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cmp x30, #EC_DABORT_LOWER_EL
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b.ne 2f
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1:
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/* Test for EA bit in the instruction syndrome */
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mrs x30, esr_el3
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tbz x30, #ESR_ISS_EABORT_EA_BIT, 2f
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handle_ea #ERROR_EA_SYNC
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2:
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/* Other kinds of synchronous exceptions are not handled */
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ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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b report_unhandled_exception
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.endm
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/* ---------------------------------------------------------------------
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* This macro handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS
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* interrupts.
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* ---------------------------------------------------------------------
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*/
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.macro handle_interrupt_exception label
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bl save_gp_registers
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/* Save the EL3 system registers needed to return from this exception */
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mrs x0, spsr_el3
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mrs x1, elr_el3
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stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
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/* Switch to the runtime stack i.e. SP_EL0 */
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ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
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mov x20, sp
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msr spsel, #0
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mov sp, x2
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/*
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* Find out whether this is a valid interrupt type.
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* If the interrupt controller reports a spurious interrupt then return
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* to where we came from.
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*/
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bl plat_ic_get_pending_interrupt_type
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cmp x0, #INTR_TYPE_INVAL
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b.eq interrupt_exit_\label
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/*
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* Get the registered handler for this interrupt type.
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* A NULL return value could be 'cause of the following conditions:
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*
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* a. An interrupt of a type was routed correctly but a handler for its
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* type was not registered.
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*
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* b. An interrupt of a type was not routed correctly so a handler for
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* its type was not registered.
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*
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* c. An interrupt of a type was routed correctly to EL3, but was
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* deasserted before its pending state could be read. Another
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* interrupt of a different type pended at the same time and its
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* type was reported as pending instead. However, a handler for this
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* type was not registered.
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*
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* a. and b. can only happen due to a programming error. The
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* occurrence of c. could be beyond the control of Trusted Firmware.
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* It makes sense to return from this exception instead of reporting an
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* error.
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*/
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bl get_interrupt_type_handler
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cbz x0, interrupt_exit_\label
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mov x21, x0
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mov x0, #INTR_ID_UNAVAILABLE
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/* Set the current security state in the 'flags' parameter */
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mrs x2, scr_el3
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ubfx x1, x2, #0, #1
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/* Restore the reference to the 'handle' i.e. SP_EL3 */
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mov x2, x20
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/* x3 will point to a cookie (not used now) */
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mov x3, xzr
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/* Call the interrupt type handler */
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blr x21
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interrupt_exit_\label:
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/* Return from exception, possibly in a different security state */
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b el3_exit
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.endm
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vector_base runtime_exceptions
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/* ---------------------------------------------------------------------
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* Current EL with SP_EL0 : 0x0 - 0x200
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* ---------------------------------------------------------------------
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*/
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vector_entry sync_exception_sp_el0
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/* We don't expect any synchronous exceptions from EL3 */
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b report_unhandled_exception
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end_vector_entry sync_exception_sp_el0
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vector_entry irq_sp_el0
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/*
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* EL3 code is non-reentrant. Any asynchronous exception is a serious
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* error. Loop infinitely.
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*/
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b report_unhandled_interrupt
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end_vector_entry irq_sp_el0
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vector_entry fiq_sp_el0
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b report_unhandled_interrupt
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end_vector_entry fiq_sp_el0
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vector_entry serror_sp_el0
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b report_unhandled_exception
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end_vector_entry serror_sp_el0
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/* ---------------------------------------------------------------------
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* Current EL with SP_ELx: 0x200 - 0x400
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* ---------------------------------------------------------------------
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*/
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vector_entry sync_exception_sp_elx
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/*
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* This exception will trigger if anything went wrong during a previous
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* exception entry or exit or while handling an earlier unexpected
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* synchronous exception. There is a high probability that SP_EL3 is
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* corrupted.
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*/
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b report_unhandled_exception
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end_vector_entry sync_exception_sp_elx
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vector_entry irq_sp_elx
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b report_unhandled_interrupt
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end_vector_entry irq_sp_elx
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vector_entry fiq_sp_elx
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b report_unhandled_interrupt
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end_vector_entry fiq_sp_elx
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vector_entry serror_sp_elx
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b report_unhandled_exception
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end_vector_entry serror_sp_elx
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/* ---------------------------------------------------------------------
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* Lower EL using AArch64 : 0x400 - 0x600
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* ---------------------------------------------------------------------
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*/
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vector_entry sync_exception_aarch64
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/*
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* This exception vector will be the entry point for SMCs and traps
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* that are unhandled at lower ELs most commonly. SP_EL3 should point
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* to a valid cpu context where the general purpose and system register
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* state can be saved.
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*/
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check_and_unmask_ea
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handle_sync_exception
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end_vector_entry sync_exception_aarch64
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vector_entry irq_aarch64
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check_and_unmask_ea
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handle_interrupt_exception irq_aarch64
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end_vector_entry irq_aarch64
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vector_entry fiq_aarch64
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check_and_unmask_ea
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handle_interrupt_exception fiq_aarch64
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end_vector_entry fiq_aarch64
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vector_entry serror_aarch64
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msr daifclr, #DAIF_ABT_BIT
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/*
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* Explicitly save x30 so as to free up a register and to enable
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* branching
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*/
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str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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handle_ea #ERROR_EA_ASYNC
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end_vector_entry serror_aarch64
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/* ---------------------------------------------------------------------
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* Lower EL using AArch32 : 0x600 - 0x800
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* ---------------------------------------------------------------------
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*/
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vector_entry sync_exception_aarch32
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/*
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* This exception vector will be the entry point for SMCs and traps
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* that are unhandled at lower ELs most commonly. SP_EL3 should point
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* to a valid cpu context where the general purpose and system register
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* state can be saved.
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*/
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check_and_unmask_ea
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handle_sync_exception
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end_vector_entry sync_exception_aarch32
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vector_entry irq_aarch32
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check_and_unmask_ea
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handle_interrupt_exception irq_aarch32
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end_vector_entry irq_aarch32
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vector_entry fiq_aarch32
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check_and_unmask_ea
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handle_interrupt_exception fiq_aarch32
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end_vector_entry fiq_aarch32
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vector_entry serror_aarch32
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msr daifclr, #DAIF_ABT_BIT
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/*
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* Explicitly save x30 so as to free up a register and to enable
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* branching
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*/
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str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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handle_ea #ERROR_EA_ASYNC
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end_vector_entry serror_aarch32
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/* ---------------------------------------------------------------------
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* This macro takes an argument in x16 that is the index in the
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* 'rt_svc_descs_indices' array, checks that the value in the array is
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* valid, and loads in x15 the pointer to the handler of that service.
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* ---------------------------------------------------------------------
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*/
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.macro load_rt_svc_desc_pointer
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/* Load descriptor index from array of indices */
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adr x14, rt_svc_descs_indices
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ldrb w15, [x14, x16]
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#if SMCCC_MAJOR_VERSION == 1
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/* Any index greater than 127 is invalid. Check bit 7. */
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tbnz w15, 7, smc_unknown
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#elif SMCCC_MAJOR_VERSION == 2
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/* Verify that the top 3 bits of the loaded index are 0 (w15 <= 31) */
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cmp w15, #31
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b.hi smc_unknown
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#endif /* SMCCC_MAJOR_VERSION */
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/*
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* Get the descriptor using the index
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* x11 = (base + off), w15 = index
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*
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* handler = (base + off) + (index << log2(size))
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*/
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adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE)
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lsl w10, w15, #RT_SVC_SIZE_LOG2
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ldr x15, [x11, w10, uxtw]
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.endm
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/* ---------------------------------------------------------------------
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* The following code handles secure monitor calls.
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* Depending upon the execution state from where the SMC has been
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* invoked, it frees some general purpose registers to perform the
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* remaining tasks. They involve finding the runtime service handler
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* that is the target of the SMC & switching to runtime stacks (SP_EL0)
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* before calling the handler.
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*
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* Note that x30 has been explicitly saved and can be used here
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* ---------------------------------------------------------------------
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*/
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func smc_handler
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smc_handler32:
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/* Check whether aarch32 issued an SMC64 */
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tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited
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smc_handler64:
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/*
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* Populate the parameters for the SMC handler.
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* We already have x0-x4 in place. x5 will point to a cookie (not used
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* now). x6 will point to the context structure (SP_EL3) and x7 will
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* contain flags we need to pass to the handler.
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*
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* Save x4-x29 and sp_el0.
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*/
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stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
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stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
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stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
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stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
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stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
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stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
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stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
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stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
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stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20]
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stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22]
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stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24]
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stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26]
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stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
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mrs x18, sp_el0
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str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0]
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mov x5, xzr
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mov x6, sp
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#if SMCCC_MAJOR_VERSION == 1
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/* Get the unique owning entity number */
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ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH
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ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH
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orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH
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load_rt_svc_desc_pointer
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#elif SMCCC_MAJOR_VERSION == 2
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/* Bit 31 must be set */
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tbz x0, #FUNCID_TYPE_SHIFT, smc_unknown
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/*
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* Check MSB of namespace to decide between compatibility/vendor and
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* SPCI/SPRT
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*/
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tbz x0, #(FUNCID_NAMESPACE_SHIFT + 1), compat_or_vendor
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/* Namespaces SPRT and SPCI currently unimplemented */
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b smc_unknown
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compat_or_vendor:
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/* Namespace is b'00 (compatibility) or b'01 (vendor) */
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/*
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* Add the LSB of the namespace (bit [28]) to the OEN [27:24] to create
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* a 5-bit index into the rt_svc_descs_indices array.
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*
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* The low 16 entries of the rt_svc_descs_indices array correspond to
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* OENs of the compatibility namespace and the top 16 entries of the
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* array are assigned to the vendor namespace descriptor.
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*/
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ubfx x16, x0, #FUNCID_OEN_SHIFT, #(FUNCID_OEN_WIDTH + 1)
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load_rt_svc_desc_pointer
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#endif /* SMCCC_MAJOR_VERSION */
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/*
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* Restore the saved C runtime stack value which will become the new
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* SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context'
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* structure prior to the last ERET from EL3.
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*/
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ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
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/* Switch to SP_EL0 */
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msr spsel, #0
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/*
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* Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there is a world
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* switch during SMC handling.
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* TODO: Revisit if all system registers can be saved later.
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*/
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mrs x16, spsr_el3
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mrs x17, elr_el3
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mrs x18, scr_el3
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stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
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str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
|
|
|
|
/* Copy SCR_EL3.NS bit to the flag to indicate caller's security */
|
|
bfi x7, x18, #0, #1
|
|
|
|
mov sp, x12
|
|
|
|
/*
|
|
* Call the Secure Monitor Call handler and then drop directly into
|
|
* el3_exit() which will program any remaining architectural state
|
|
* prior to issuing the ERET to the desired lower EL.
|
|
*/
|
|
#if DEBUG
|
|
cbz x15, rt_svc_fw_critical_error
|
|
#endif
|
|
blr x15
|
|
|
|
b el3_exit
|
|
|
|
smc_unknown:
|
|
/*
|
|
* Unknown SMC call. Populate return value with SMC_UNK, restore
|
|
* GP registers, and return to caller.
|
|
*/
|
|
mov x0, #SMC_UNK
|
|
str x0, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
|
|
b restore_gp_registers_eret
|
|
|
|
smc_prohibited:
|
|
ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
|
|
mov x0, #SMC_UNK
|
|
eret
|
|
|
|
rt_svc_fw_critical_error:
|
|
/* Switch to SP_ELx */
|
|
msr spsel, #1
|
|
no_ret report_unhandled_exception
|
|
endfunc smc_handler
|
|
|
|
/*
|
|
* Delegate External Abort handling to platform's EA handler. This function
|
|
* assumes that all GP registers have been saved by the caller.
|
|
*
|
|
* x0: EA reason
|
|
* x1: EA syndrome
|
|
*/
|
|
func delegate_ea
|
|
/* Save EL3 state */
|
|
mrs x2, spsr_el3
|
|
mrs x3, elr_el3
|
|
stp x2, x3, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
|
|
|
|
/*
|
|
* Save ESR as handling might involve lower ELs, and returning back to
|
|
* EL3 from there would trample the original ESR.
|
|
*/
|
|
mrs x4, scr_el3
|
|
mrs x5, esr_el3
|
|
stp x4, x5, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
|
|
|
|
/*
|
|
* Setup rest of arguments, and call platform External Abort handler.
|
|
*
|
|
* x0: EA reason (already in place)
|
|
* x1: Exception syndrome (already in place).
|
|
* x2: Cookie (unused for now).
|
|
* x3: Context pointer.
|
|
* x4: Flags (security state from SCR for now).
|
|
*/
|
|
mov x2, xzr
|
|
mov x3, sp
|
|
ubfx x4, x4, #0, #1
|
|
|
|
/* Switch to runtime stack */
|
|
ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
|
|
msr spsel, #0
|
|
mov sp, x5
|
|
|
|
mov x29, x30
|
|
bl plat_ea_handler
|
|
mov x30, x29
|
|
|
|
/* Make SP point to context */
|
|
msr spsel, #1
|
|
|
|
/* Restore EL3 state */
|
|
ldp x1, x2, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
|
|
msr spsr_el3, x1
|
|
msr elr_el3, x2
|
|
|
|
/* Restore ESR_EL3 and SCR_EL3 */
|
|
ldp x3, x4, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
|
|
msr scr_el3, x3
|
|
msr esr_el3, x4
|
|
|
|
ret
|
|
endfunc delegate_ea
|