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a8d5d3d540
At the moment we have some elaborate, but very schematic functions to allow checking for CPU feature enablement. Adding some more becomes tedious and is also error-prone. Provide two wrapper macros that reduce most of the features to a single line: - CREATE_FEATURE_FUNCS(name, idreg, idfield, guard) creates two functions read_<name>_id_field() and is_<name>_supported(), that check the 4-bit CPU ID field starting at bit <idfield> in <idreg> for being not 0, and compares it against the build time <guard> symbol. For the usual feature (like PAN) this looks like: CREATE_FEATURE_FUNCS(feat_pan, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_PAN_SHIFT, ENABLE_FEAT_PAN) - CREATE_FEATURE_FUNCS_VER(name, read_func, idvalue, guard) creates one function to check for a certain CPU ID field *value*, so when "!= 0" is not sufficient. It's meant to be used in addition to the above macro, since that generates the CPU ID field accessor function: CREATE_FEATURE_FUNCS(feat_amu, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT, ENABLE_FEAT_AMU) CREATE_FEATURE_FUNCS_VER(feat_amuv1p1, read_feat_amu_id_field, ID_AA64PFR0_AMU_V1P1, ENABLE_FEAT_AMUv1p1) Describe the existing feature accessor functions using those new macros, to reduce the size of the file, improve readability and decrease the possibility of (copy&paste) bugs. Change-Id: Ib136a875b4857058ff561c4635ace344006f29bf Signed-off-by: Andre Przywara <andre.przywara@arm.com>
293 lines
9.4 KiB
C
293 lines
9.4 KiB
C
/*
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* Copyright (c) 2019-2023, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ARCH_FEATURES_H
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#define ARCH_FEATURES_H
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#include <stdbool.h>
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#include <arch_helpers.h>
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#include <common/feat_detect.h>
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#define ISOLATE_FIELD(reg, feat) \
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((unsigned int)(((reg) >> (feat)) & ID_REG_FIELD_MASK))
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#define CREATE_FEATURE_FUNCS_VER(name, read_func, idvalue, guard) \
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static inline bool is_ ## name ## _supported(void) \
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{ \
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if ((guard) == FEAT_STATE_DISABLED) { \
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return false; \
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} \
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if ((guard) == FEAT_STATE_ALWAYS) { \
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return true; \
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} \
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return read_func() >= (idvalue); \
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}
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#define CREATE_FEATURE_FUNCS(name, idreg, idfield, guard) \
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static unsigned int read_ ## name ## _id_field(void) \
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{ \
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return ISOLATE_FIELD(read_ ## idreg(), idfield); \
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} \
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CREATE_FEATURE_FUNCS_VER(name, read_ ## name ## _id_field, 1U, guard)
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static inline bool is_armv7_gentimer_present(void)
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{
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/* The Generic Timer is always present in an ARMv8-A implementation */
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return true;
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}
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CREATE_FEATURE_FUNCS(feat_pan, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_PAN_SHIFT,
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ENABLE_FEAT_PAN)
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CREATE_FEATURE_FUNCS(feat_vhe, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_VHE_SHIFT,
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ENABLE_FEAT_VHE)
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static inline bool is_armv8_2_ttcnp_present(void)
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{
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return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_CNP_SHIFT) &
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ID_AA64MMFR2_EL1_CNP_MASK) != 0U;
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}
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static inline bool is_feat_pacqarma3_present(void)
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{
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uint64_t mask_id_aa64isar2 =
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(ID_AA64ISAR2_GPA3_MASK << ID_AA64ISAR2_GPA3_SHIFT) |
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(ID_AA64ISAR2_APA3_MASK << ID_AA64ISAR2_APA3_SHIFT);
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/* If any of the fields is not zero, QARMA3 algorithm is present */
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return (read_id_aa64isar2_el1() & mask_id_aa64isar2) != 0U;
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}
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static inline bool is_armv8_3_pauth_present(void)
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{
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uint64_t mask_id_aa64isar1 =
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(ID_AA64ISAR1_GPI_MASK << ID_AA64ISAR1_GPI_SHIFT) |
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(ID_AA64ISAR1_GPA_MASK << ID_AA64ISAR1_GPA_SHIFT) |
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(ID_AA64ISAR1_API_MASK << ID_AA64ISAR1_API_SHIFT) |
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(ID_AA64ISAR1_APA_MASK << ID_AA64ISAR1_APA_SHIFT);
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/*
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* If any of the fields is not zero or QARMA3 is present,
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* PAuth is present
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*/
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return ((read_id_aa64isar1_el1() & mask_id_aa64isar1) != 0U ||
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is_feat_pacqarma3_present());
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}
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static inline bool is_armv8_4_ttst_present(void)
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{
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return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_ST_SHIFT) &
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ID_AA64MMFR2_EL1_ST_MASK) == 1U;
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}
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static inline bool is_armv8_5_bti_present(void)
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{
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return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_BT_SHIFT) &
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ID_AA64PFR1_EL1_BT_MASK) == BTI_IMPLEMENTED;
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}
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static inline unsigned int get_armv8_5_mte_support(void)
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{
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return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_MTE_SHIFT) &
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ID_AA64PFR1_EL1_MTE_MASK);
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}
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CREATE_FEATURE_FUNCS(feat_sel2, id_aa64pfr0_el1, ID_AA64PFR0_SEL2_SHIFT,
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ENABLE_FEAT_SEL2)
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CREATE_FEATURE_FUNCS(feat_twed, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_TWED_SHIFT,
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ENABLE_FEAT_TWED)
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CREATE_FEATURE_FUNCS(feat_fgt, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT,
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ENABLE_FEAT_FGT)
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CREATE_FEATURE_FUNCS(feat_mte_perm, id_aa64pfr2_el1,
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ID_AA64PFR2_EL1_MTEPERM_SHIFT, ENABLE_FEAT_MTE_PERM)
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CREATE_FEATURE_FUNCS(feat_ecv, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT,
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ENABLE_FEAT_ECV)
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CREATE_FEATURE_FUNCS_VER(feat_ecv_v2, read_feat_ecv_id_field,
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ID_AA64MMFR0_EL1_ECV_SELF_SYNCH, ENABLE_FEAT_ECV)
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CREATE_FEATURE_FUNCS(feat_rng, id_aa64isar0_el1, ID_AA64ISAR0_RNDR_SHIFT,
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ENABLE_FEAT_RNG)
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CREATE_FEATURE_FUNCS(feat_tcr2, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_TCRX_SHIFT,
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ENABLE_FEAT_TCR2)
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CREATE_FEATURE_FUNCS(feat_s2poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2POE_SHIFT,
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ENABLE_FEAT_S2POE)
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CREATE_FEATURE_FUNCS(feat_s1poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1POE_SHIFT,
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ENABLE_FEAT_S1POE)
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static inline bool is_feat_sxpoe_supported(void)
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{
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return is_feat_s1poe_supported() || is_feat_s2poe_supported();
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}
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CREATE_FEATURE_FUNCS(feat_s2pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2PIE_SHIFT,
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ENABLE_FEAT_S2PIE)
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CREATE_FEATURE_FUNCS(feat_s1pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1PIE_SHIFT,
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ENABLE_FEAT_S1PIE)
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static inline bool is_feat_sxpie_supported(void)
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{
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return is_feat_s1pie_supported() || is_feat_s2pie_supported();
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}
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/* FEAT_GCS: Guarded Control Stack */
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CREATE_FEATURE_FUNCS(feat_gcs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_GCS_SHIFT,
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ENABLE_FEAT_GCS)
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/* FEAT_AMU: Activity Monitors Extension */
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CREATE_FEATURE_FUNCS(feat_amu, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT,
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ENABLE_FEAT_AMU)
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CREATE_FEATURE_FUNCS_VER(feat_amuv1p1, read_feat_amu_id_field,
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ID_AA64PFR0_AMU_V1P1, ENABLE_FEAT_AMUv1p1)
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/*
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* Return MPAM version:
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*
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* 0x00: None Armv8.0 or later
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* 0x01: v0.1 Armv8.4 or later
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* 0x10: v1.0 Armv8.2 or later
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* 0x11: v1.1 Armv8.4 or later
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*
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*/
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static inline unsigned int read_feat_mpam_version(void)
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{
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return (unsigned int)((((read_id_aa64pfr0_el1() >>
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ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) |
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((read_id_aa64pfr1_el1() >>
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ID_AA64PFR1_MPAM_FRAC_SHIFT) & ID_AA64PFR1_MPAM_FRAC_MASK));
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}
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CREATE_FEATURE_FUNCS_VER(feat_mpam, read_feat_mpam_version, 1U,
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ENABLE_MPAM_FOR_LOWER_ELS)
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/* FEAT_HCX: Extended Hypervisor Configuration Register */
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CREATE_FEATURE_FUNCS(feat_hcx, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_HCX_SHIFT,
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ENABLE_FEAT_HCX)
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static inline bool is_feat_rng_trap_present(void)
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{
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return (((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT) &
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ID_AA64PFR1_EL1_RNDR_TRAP_MASK)
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== ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED);
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}
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static inline unsigned int get_armv9_2_feat_rme_support(void)
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{
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/*
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* Return the RME version, zero if not supported. This function can be
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* used as both an integer value for the RME version or compared to zero
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* to detect RME presence.
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*/
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return (unsigned int)(read_id_aa64pfr0_el1() >>
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ID_AA64PFR0_FEAT_RME_SHIFT) & ID_AA64PFR0_FEAT_RME_MASK;
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}
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/*********************************************************************************
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* Function to identify the presence of FEAT_SB (Speculation Barrier Instruction)
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********************************************************************************/
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static inline unsigned int read_feat_sb_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB_SHIFT);
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}
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/* FEAT_CSV2_2: Cache Speculation Variant 2 */
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CREATE_FEATURE_FUNCS(feat_csv2, id_aa64pfr0_el1, ID_AA64PFR0_CSV2_SHIFT, 0)
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CREATE_FEATURE_FUNCS_VER(feat_csv2_2, read_feat_csv2_id_field,
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ID_AA64PFR0_CSV2_2_SUPPORTED, ENABLE_FEAT_CSV2_2)
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/* FEAT_SPE: Statistical Profiling Extension */
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CREATE_FEATURE_FUNCS(feat_spe, id_aa64dfr0_el1, ID_AA64DFR0_PMS_SHIFT,
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ENABLE_SPE_FOR_NS)
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/* FEAT_SVE: Scalable Vector Extension */
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CREATE_FEATURE_FUNCS(feat_sve, id_aa64pfr0_el1, ID_AA64PFR0_SVE_SHIFT,
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ENABLE_SVE_FOR_NS)
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/* FEAT_RAS: Reliability, Accessibility, Serviceability */
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CREATE_FEATURE_FUNCS(feat_ras, id_aa64pfr0_el1,
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ID_AA64PFR0_RAS_SHIFT, ENABLE_FEAT_RAS)
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/* FEAT_DIT: Data Independent Timing instructions */
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CREATE_FEATURE_FUNCS(feat_dit, id_aa64pfr0_el1,
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ID_AA64PFR0_DIT_SHIFT, ENABLE_FEAT_DIT)
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CREATE_FEATURE_FUNCS(feat_sys_reg_trace, id_aa64dfr0_el1,
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ID_AA64DFR0_TRACEVER_SHIFT, ENABLE_SYS_REG_TRACE_FOR_NS)
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/* FEAT_TRF: TraceFilter */
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CREATE_FEATURE_FUNCS(feat_trf, id_aa64dfr0_el1, ID_AA64DFR0_TRACEFILT_SHIFT,
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ENABLE_TRF_FOR_NS)
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/* FEAT_NV2: Enhanced Nested Virtualization */
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CREATE_FEATURE_FUNCS(feat_nv, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT, 0)
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CREATE_FEATURE_FUNCS_VER(feat_nv2, read_feat_nv_id_field,
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ID_AA64MMFR2_EL1_NV2_SUPPORTED, CTX_INCLUDE_NEVE_REGS)
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/* FEAT_BRBE: Branch Record Buffer Extension */
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CREATE_FEATURE_FUNCS(feat_brbe, id_aa64dfr0_el1, ID_AA64DFR0_BRBE_SHIFT,
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ENABLE_BRBE_FOR_NS)
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/* FEAT_TRBE: Trace Buffer Extension */
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CREATE_FEATURE_FUNCS(feat_trbe, id_aa64dfr0_el1, ID_AA64DFR0_TRACEBUFFER_SHIFT,
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ENABLE_TRBE_FOR_NS)
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static inline unsigned int read_feat_sme_fa64_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64smfr0_el1(),
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ID_AA64SMFR0_EL1_SME_FA64_SHIFT);
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}
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/* FEAT_SMEx: Scalar Matrix Extension */
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CREATE_FEATURE_FUNCS(feat_sme, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT,
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ENABLE_SME_FOR_NS)
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CREATE_FEATURE_FUNCS_VER(feat_sme2, read_feat_sme_id_field,
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ID_AA64PFR1_EL1_SME2_SUPPORTED, ENABLE_SME2_FOR_NS)
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/*******************************************************************************
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* Function to get hardware granularity support
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******************************************************************************/
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static inline unsigned int read_id_aa64mmfr0_el0_tgran4_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
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ID_AA64MMFR0_EL1_TGRAN4_SHIFT);
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}
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static inline unsigned int read_id_aa64mmfr0_el0_tgran16_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
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ID_AA64MMFR0_EL1_TGRAN16_SHIFT);
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}
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static inline unsigned int read_id_aa64mmfr0_el0_tgran64_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
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ID_AA64MMFR0_EL1_TGRAN64_SHIFT);
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}
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static inline unsigned int read_feat_pmuv3_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMUVER_SHIFT);
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}
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static inline unsigned int read_feat_mtpmu_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT);
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}
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static inline bool is_feat_mtpmu_supported(void)
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{
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if (DISABLE_MTPMU == FEAT_STATE_DISABLED) {
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return false;
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}
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if (DISABLE_MTPMU == FEAT_STATE_ALWAYS) {
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return true;
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}
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unsigned int mtpmu = read_feat_mtpmu_id_field();
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return (mtpmu != 0U) && (mtpmu != ID_AA64DFR0_MTPMU_DISABLED);
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}
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#endif /* ARCH_FEATURES_H */
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