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MPMM - the Maximum Power Mitigation Mechanism - is an optional microarchitectural feature present on some Armv9-A cores, introduced with the Cortex-X2, Cortex-A710 and Cortex-A510 cores. MPMM allows the SoC firmware to detect and limit high activity events to assist in SoC processor power domain dynamic power budgeting and limit the triggering of whole-rail (i.e. clock chopping) responses to overcurrent conditions. This feature is enabled via the `ENABLE_MPMM` build option. Configuration can be done via FCONF by enabling `ENABLE_MPMM_FCONF`, or by via the plaform-implemented `plat_mpmm_topology` function. Change-Id: I77da82808ad4744ece8263f0bf215c5a091c3167 Signed-off-by: Chris Kay <chris.kay@arm.com>
57 lines
1.3 KiB
C
57 lines
1.3 KiB
C
/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MPMM_H
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#define MPMM_H
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#include <stdbool.h>
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#include <platform_def.h>
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/*
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* Enable the Maximum Power Mitigation Mechanism.
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*
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* This function will enable MPMM for the current core. The AMU counters
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* representing the MPMM gears must have been configured and enabled prior to
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* calling this function.
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*/
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void mpmm_enable(void);
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/*
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* MPMM core data.
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*
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* This structure represents per-core data retrieved from the hardware
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* configuration device tree.
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*/
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struct mpmm_core {
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/*
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* Whether MPMM is supported.
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*
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* Cores with support for MPMM offer one or more auxiliary AMU counters
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* representing MPMM gears.
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*/
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bool supported;
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};
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/*
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* MPMM topology.
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*
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* This topology structure describes the system-wide representation of the
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* information retrieved from the hardware configuration device tree.
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*/
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struct mpmm_topology {
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struct mpmm_core cores[PLATFORM_CORE_COUNT]; /* Per-core data */
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};
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#if !ENABLE_MPMM_FCONF
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/*
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* Retrieve the platform's MPMM topology. A `NULL` return value is treated as a
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* non-fatal error, in which case MPMM will not be enabled for any core.
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*/
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const struct mpmm_topology *plat_mpmm_topology(void);
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#endif /* ENABLE_MPMM_FCONF */
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#endif /* MPMM_H */
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