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MPMM - the Maximum Power Mitigation Mechanism - is an optional microarchitectural feature present on some Armv9-A cores, introduced with the Cortex-X2, Cortex-A710 and Cortex-A510 cores. MPMM allows the SoC firmware to detect and limit high activity events to assist in SoC processor power domain dynamic power budgeting and limit the triggering of whole-rail (i.e. clock chopping) responses to overcurrent conditions. This feature is enabled via the `ENABLE_MPMM` build option. Configuration can be done via FCONF by enabling `ENABLE_MPMM_FCONF`, or by via the plaform-implemented `plat_mpmm_topology` function. Change-Id: I77da82808ad4744ece8263f0bf215c5a091c3167 Signed-off-by: Chris Kay <chris.kay@arm.com>
20 lines
403 B
C
20 lines
403 B
C
/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef FCONF_MPMM_GETTER_H
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#define FCONF_MPMM_GETTER_H
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#include <lib/mpmm/mpmm.h>
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#define mpmm__config_getter(id) fconf_mpmm_config.id
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struct fconf_mpmm_config {
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const struct mpmm_topology *topology;
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};
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extern struct fconf_mpmm_config fconf_mpmm_config;
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#endif /* FCONF_MPMM_GETTER_H */
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