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MPMM - the Maximum Power Mitigation Mechanism - is an optional microarchitectural feature present on some Armv9-A cores, introduced with the Cortex-X2, Cortex-A710 and Cortex-A510 cores. MPMM allows the SoC firmware to detect and limit high activity events to assist in SoC processor power domain dynamic power budgeting and limit the triggering of whole-rail (i.e. clock chopping) responses to overcurrent conditions. This feature is enabled via the `ENABLE_MPMM` build option. Configuration can be done via FCONF by enabling `ENABLE_MPMM_FCONF`, or by via the plaform-implemented `plat_mpmm_topology` function. Change-Id: I77da82808ad4744ece8263f0bf215c5a091c3167 Signed-off-by: Chris Kay <chris.kay@arm.com>
48 lines
1.3 KiB
ReStructuredText
48 lines
1.3 KiB
ReStructuredText
Maximum Power Mitigation Mechanism (MPMM) Bindings
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==================================================
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|MPMM| support cannot be determined at runtime by the firmware. Instead, these
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DTB bindings allow the platform to communicate per-core support for |MPMM| via
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the ``HW_CONFIG`` device tree blob.
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Bindings
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^^^^^^^^
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.. contents::
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:local:
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``/cpus/cpus/cpu*`` node properties
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"""""""""""""""""""""""""""""""""""
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The ``cpu`` node has been augmented to allow the platform to indicate support
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for |MPMM| on a given core.
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+-------------------+-------+-------------+------------------------------------+
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| Property name | Usage | Value type | Description |
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+===================+=======+=============+====================================+
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| ``supports-mpmm`` | O | ``<empty>`` | If present, indicates that |MPMM| |
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| | | | is available on this core. |
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+-------------------+-------+-------------+------------------------------------+
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Example
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^^^^^^^
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An example system offering two cores, one with support for |MPMM| and one
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without, can be described as follows:
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.. code-block::
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0@00000 {
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...
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supports-mpmm;
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};
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cpu1@00100 {
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...
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};
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}
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