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https://github.com/ARM-software/arm-trusted-firmware.git
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a806dad58c
There are many instances in ARM Trusted Firmware where control is transferred to functions from which return isn't expected. Such jumps are made using 'bl' instruction to provide the callee with the location from which it was jumped to. Additionally, debuggers infer the caller by examining where 'lr' register points to. If a 'bl' of the nature described above falls at the end of an assembly function, 'lr' will be left pointing to a location outside of the function range. This misleads the debugger back trace. This patch defines a 'no_ret' macro to be used when jumping to functions from which return isn't expected. The macro ensures to use 'bl' instruction for the jump, and also, for debug builds, places a 'nop' instruction immediately thereafter (unless instructed otherwise) so as to leave 'lr' pointing within the function range. Change-Id: Ib34c69fc09197cfd57bc06e147cc8252910e01b0 Co-authored-by: Douglas Raillard <douglas.raillard@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
201 lines
6.7 KiB
ArmAsm
201 lines
6.7 KiB
ArmAsm
/*
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* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <gicv2.h>
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#include <gicv3.h>
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#include <platform_def.h>
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#include <v2m_def.h>
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#include "../drivers/pwrc/fvp_pwrc.h"
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#include "../fvp_def.h"
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.globl plat_secondary_cold_boot_setup
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.globl plat_get_my_entrypoint
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.globl plat_is_my_cpu_primary
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.macro fvp_choose_gicmmap param1, param2, x_tmp, w_tmp, res
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ldr \x_tmp, =V2M_SYSREGS_BASE + V2M_SYS_ID
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ldr \w_tmp, [\x_tmp]
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ubfx \w_tmp, \w_tmp, #V2M_SYS_ID_BLD_SHIFT, #V2M_SYS_ID_BLD_LENGTH
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cmp \w_tmp, #BLD_GIC_VE_MMAP
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csel \res, \param1, \param2, eq
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.endm
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/* -----------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset e.g
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* mark the cpu's presence, mechanism to place it in a
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* holding pen etc.
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* TODO: Should we read the PSYS register to make sure
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* that the request has gone through.
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* -----------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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#ifndef EL3_PAYLOAD_BASE
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/* ---------------------------------------------
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* Power down this cpu.
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* TODO: Do we need to worry about powering the
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* cluster down as well here. That will need
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* locks which we won't have unless an elf-
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* loader zeroes out the zi section.
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* ---------------------------------------------
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*/
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mrs x0, mpidr_el1
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ldr x1, =PWRC_BASE
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str w0, [x1, #PPOFFR_OFF]
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/* ---------------------------------------------
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* Disable GIC bypass as well
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* ---------------------------------------------
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*/
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/* Check for GICv3 system register access */
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mrs x0, id_aa64pfr0_el1
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ubfx x0, x0, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
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cmp x0, #1
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b.ne gicv2_bypass_disable
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/* Check for SRE enable */
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mrs x1, ICC_SRE_EL3
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tst x1, #ICC_SRE_SRE_BIT
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b.eq gicv2_bypass_disable
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mrs x2, ICC_SRE_EL3
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orr x2, x2, #(ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)
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msr ICC_SRE_EL3, x2
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b secondary_cold_boot_wait
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gicv2_bypass_disable:
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ldr x0, =VE_GICC_BASE
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ldr x1, =BASE_GICC_BASE
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fvp_choose_gicmmap x0, x1, x2, w2, x1
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mov w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1)
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orr w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0)
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str w0, [x1, #GICC_CTLR]
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secondary_cold_boot_wait:
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/* ---------------------------------------------
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* There is no sane reason to come out of this
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* wfi so panic if we do. This cpu will be pow-
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* ered on and reset by the cpu_on pm api
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* ---------------------------------------------
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*/
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dsb sy
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wfi
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no_ret plat_panic_handler
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#else
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mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
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/* Wait until the entrypoint gets populated */
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poll_mailbox:
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ldr x1, [x0]
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cbz x1, 1f
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br x1
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1:
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wfe
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b poll_mailbox
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#endif /* EL3_PAYLOAD_BASE */
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endfunc plat_secondary_cold_boot_setup
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/* ---------------------------------------------------------------------
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* uintptr_t plat_get_my_entrypoint (void);
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*
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* Main job of this routine is to distinguish between a cold and warm
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* boot. On FVP, this information can be queried from the power
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* controller. The Power Control SYS Status Register (PSYSR) indicates
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* the wake-up reason for the CPU.
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*
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* For a cold boot, return 0.
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* For a warm boot, read the mailbox and return the address it contains.
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*
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* TODO: PSYSR is a common register and should be
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* accessed using locks. Since it is not possible
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* to use locks immediately after a cold reset
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* we are relying on the fact that after a cold
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* reset all cpus will read the same WK field
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* ---------------------------------------------------------------------
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*/
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func plat_get_my_entrypoint
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/* ---------------------------------------------------------------------
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* When bit PSYSR.WK indicates either "Wake by PPONR" or "Wake by GIC
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* WakeRequest signal" then it is a warm boot.
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* ---------------------------------------------------------------------
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*/
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mrs x2, mpidr_el1
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ldr x1, =PWRC_BASE
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str w2, [x1, #PSYSR_OFF]
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ldr w2, [x1, #PSYSR_OFF]
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ubfx w2, w2, #PSYSR_WK_SHIFT, #PSYSR_WK_WIDTH
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cmp w2, #WKUP_PPONR
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beq warm_reset
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cmp w2, #WKUP_GICREQ
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beq warm_reset
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/* Cold reset */
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mov x0, #0
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ret
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warm_reset:
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/* ---------------------------------------------------------------------
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* A mailbox is maintained in the trusted SRAM. It is flushed out of the
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* caches after every update using normal memory so it is safe to read
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* it here with SO attributes.
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* ---------------------------------------------------------------------
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*/
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mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
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ldr x0, [x0]
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cbz x0, _panic_handler
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ret
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/* ---------------------------------------------------------------------
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* The power controller indicates this is a warm reset but the mailbox
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* is empty. This should never happen!
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* ---------------------------------------------------------------------
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*/
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_panic_handler:
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no_ret plat_panic_handler
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endfunc plat_get_my_entrypoint
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/* -----------------------------------------------------
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* unsigned int plat_is_my_cpu_primary (void);
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*
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* Find out whether the current cpu is the primary
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* cpu.
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* -----------------------------------------------------
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*/
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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cmp x0, #FVP_PRIMARY_CPU
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cset w0, eq
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ret
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endfunc plat_is_my_cpu_primary
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