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a67c1b1b2b
Cortex-A510 erratum 2371937 is a Cat B erratum that applies to revisions r0p0, r0p1, r0p2, r0p3, r1p0, and r1p1. It is fixed in r1p2. The workaround is to set the ATOM field of CPUECTLR_EL1 (bits [40:38]) to 0b010, which will force all cacheable atomic operations to be executed near. SDEN can be found here: https://developer.arm.com/documentation/SDEN1873351/latest https://developer.arm.com/documentation/SDEN1873361/latest Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com> Change-Id: Ia219a609a3397e39631de65831ecff8a3cd1227e |
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| _static/css | ||
| about | ||
| components | ||
| design | ||
| design_documents | ||
| getting_started | ||
| perf | ||
| plat | ||
| process | ||
| resources | ||
| security_advisories | ||
| threat_model | ||
| change-log.md | ||
| conf.py | ||
| global_substitutions.txt | ||
| glossary.rst | ||
| index.rst | ||
| license.rst | ||
| Makefile | ||
| requirements.in | ||
| requirements.txt | ||