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a658b46dc7
Compile-time controls have been added for the following: * SCMI power domain use for DPU and GPU. * SMMU-700: planned rework required to use IOMMU correctly for DPU and GPU. These will allow easier experimentation in the future without ad-hoc changes needed in the dts file for any sort of analysis that requires testing different paths. For TC3 however, the DPU is in an always on power domain so SCMI power domains are not supported. Co-developed-by: Tintu Thomas <tintu.thomas@arm.com> Signed-off-by: Kshitij Sisodia <kshitij.sisodia@arm.com> Change-Id: If6179a3e4784c1b69f0338a8d52b552452c0eac1
138 lines
3.7 KiB
Text
138 lines
3.7 KiB
Text
/*
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* Copyright (c) 2023-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/* If SCMI power domain control is enabled */
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#if TC_SCMI_PD_CTRL_EN
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#define GPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 1)
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#define DPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 2)
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#endif /* TC_SCMI_PD_CTRL_EN */
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/* All perf is normalized against the big core */
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#define BIG_CAPACITY 1024
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#if TARGET_PLATFORM <= 2
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#if TARGET_FLAVOUR_FVP
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#define LIT_CAPACITY 406
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#define MID_CAPACITY 912
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#else /* TARGET_FLAVOUR_FPGA */
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#define LIT_CAPACITY 280
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#define MID_CAPACITY 775
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/* this is an area optimized configuration of the big core */
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#define BIG2_CAPACITY 930
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#endif /* TARGET_FLAVOUR_FPGA */
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#define INT_MBOX_RX 317
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#define MHU_TX_ADDR(pref) pref##45000000 /* hex */
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#define MHU_RX_ADDR(pref) pref##45010000 /* hex */
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#define MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */
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#define UARTCLK_FREQ 5000000
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#elif TARGET_PLATFORM == 3
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#define LIT_CAPACITY 239
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#define MID_CAPACITY 686
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#define INT_MBOX_RX 300
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#define MHU_TX_ADDR(pref) pref##46040000 /* hex */
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#define MHU_RX_ADDR(pref) pref##46140000 /* hex */
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#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
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#define UARTCLK_FREQ 3750000
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#endif /* TARGET_PLATFORM == 3 */
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#if TARGET_FLAVOUR_FVP
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#define STDOUT_PATH "serial0:115200n8"
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#define GIC_CTRL_ADDR 2c010000
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#define GIC_GICR_OFFSET 0x200000
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#define UART_OFFSET 0x1000
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#define VENCODER_TIMING_CLK 25175000
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#define VENCODER_TIMING \
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clock-frequency = <VENCODER_TIMING_CLK>; \
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hactive = <640>; \
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vactive = <480>; \
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hfront-porch = <16>; \
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hback-porch = <48>; \
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hsync-len = <96>; \
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vfront-porch = <10>; \
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vback-porch = <33>; \
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vsync-len = <2>
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#define ETH_COMPATIBLE "smsc,lan91c111"
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#define MMC_REMOVABLE cd-gpios = <&sysreg 0 0>
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#else /* TARGET_FLAVOUR_FPGA */
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#define STDOUT_PATH "serial0:38400n8"
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#define GIC_CTRL_ADDR 30000000
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#define GIC_GICR_OFFSET 0x1000000
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#define UART_OFFSET 0x10000
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/* 1440x3200@120 framebuffer */
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#define VENCODER_TIMING_CLK 836000000
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#define VENCODER_TIMING \
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clock-frequency = <VENCODER_TIMING_CLK>; \
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hactive = <1440>; \
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vactive = <3200>; \
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hfront-porch = <136>; \
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hback-porch = <296>; \
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hsync-len = <160>; \
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vfront-porch = <3>; \
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vback-porch = <217>; \
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vsync-len = <10>
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#define ETH_COMPATIBLE "smsc,lan9115"
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#define MMC_REMOVABLE non-removable
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#endif /* TARGET_FLAVOUR_FPGA */
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/* Use SCMI controlled clocks */
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#if TC_DPU_USE_SCMI_CLK
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#define DPU_CLK_ATTR1 \
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clocks = <&scmi_clk 0>; \
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clock-names = "aclk"
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#define DPU_CLK_ATTR2 \
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clocks = <&scmi_clk 1>; \
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clock-names = "pxclk"
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#define DPU_CLK_ATTR3 \
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clocks = <&scmi_clk 2>; \
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clock-names = "pxclk" \
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/* Use fixed clocks */
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#else /* !TC_DPU_USE_SCMI_CLK */
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#define DPU_CLK_ATTR1 \
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clocks = <&dpu_aclk>; \
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clock-names = "aclk"
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#define DPU_CLK_ATTR2 \
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clocks = <&dpu_pixel_clk>, <&dpu_aclk>; \
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clock-names = "pxclk", "aclk"
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#define DPU_CLK_ATTR3 DPU_CLK_ATTR2
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#endif /* !TC_DPU_USE_SCMI_CLK */
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/ {
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#if TARGET_PLATFORM <= 2
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cmn-pmu {
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compatible = "arm,ci-700";
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reg = <0x0 0x50000000 0x0 0x10000000>;
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interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
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};
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#endif /* TARGET_PLATFORM <= 2 */
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#if !TC_DPU_USE_SCMI_CLK
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dpu_aclk: dpu_aclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <VENCODER_TIMING_CLK>;
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clock-output-names = "fpga:dpu_aclk";
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};
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dpu_pixel_clk: dpu-pixel-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <VENCODER_TIMING_CLK>;
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clock-output-names = "pxclk";
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};
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#endif /* !TC_DPU_USE_SCMI_CLK */
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};
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