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https://github.com/ARM-software/arm-trusted-firmware.git
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a658b46dc7
Compile-time controls have been added for the following: * SCMI power domain use for DPU and GPU. * SMMU-700: planned rework required to use IOMMU correctly for DPU and GPU. These will allow easier experimentation in the future without ad-hoc changes needed in the dts file for any sort of analysis that requires testing different paths. For TC3 however, the DPU is in an always on power domain so SCMI power domains are not supported. Co-developed-by: Tintu Thomas <tintu.thomas@arm.com> Signed-off-by: Kshitij Sisodia <kshitij.sisodia@arm.com> Change-Id: If6179a3e4784c1b69f0338a8d52b552452c0eac1
746 lines
16 KiB
Text
746 lines
16 KiB
Text
/*
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* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "platform_def.h"
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#include "tc_vers.dtsi"
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#if TARGET_FLAVOUR_FVP
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#include "tc_fvp.dtsi"
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#endif /* TARGET_FLAVOUR_FVP */
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/ {
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compatible = "arm,tc";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &os_uart;
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};
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chosen {
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stdout-path = STDOUT_PATH;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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core4 {
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cpu = <&CPU4>;
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};
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core5 {
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cpu = <&CPU5>;
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};
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core6 {
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cpu = <&CPU6>;
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};
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core7 {
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cpu = <&CPU7>;
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};
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#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
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core8 {
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cpu = <&CPU8>;
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};
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core9 {
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cpu = <&CPU9>;
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};
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core10 {
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cpu = <&CPU10>;
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};
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core11 {
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cpu = <&CPU11>;
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};
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core12 {
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cpu = <&CPU12>;
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};
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core13 {
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cpu = <&CPU13>;
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};
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#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
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};
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};
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/*
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* The timings below are just to demonstrate working cpuidle.
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* These values may be inaccurate.
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*/
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idle-states {
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entry-method = "psci";
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CPU_SLEEP_0: cpu-sleep-0 {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x0010000>;
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local-timer-stop;
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entry-latency-us = <300>;
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exit-latency-us = <1200>;
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min-residency-us = <2000>;
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};
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CLUSTER_SLEEP_0: cluster-sleep-0 {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x1010000>;
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local-timer-stop;
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entry-latency-us = <400>;
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exit-latency-us = <1200>;
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min-residency-us = <2500>;
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};
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};
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amus {
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amu: amu-0 {
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#address-cells = <1>;
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#size-cells = <0>;
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mpmm_gear0: counter@0 {
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reg = <0>;
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enable-at-el3;
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};
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mpmm_gear1: counter@1 {
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reg = <1>;
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enable-at-el3;
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};
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mpmm_gear2: counter@2 {
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reg = <2>;
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enable-at-el3;
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};
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};
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};
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CPU0:cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 0>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <LIT_CAPACITY>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU1:cpu@100 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x100>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 0>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <LIT_CAPACITY>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU2:cpu@200 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x200>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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#if TARGET_PLATFORM <= 2
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clocks = <&scmi_dvfs 0>;
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capacity-dmips-mhz = <LIT_CAPACITY>;
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#elif TARGET_PLATFORM == 3
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clocks = <&scmi_dvfs 1>;
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capacity-dmips-mhz = <MID_CAPACITY>;
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#endif /* TARGET_PLATFORM == 3 */
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amu = <&amu>;
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supports-mpmm;
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};
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CPU3:cpu@300 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x300>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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#if TARGET_PLATFORM <= 2
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clocks = <&scmi_dvfs 0>;
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capacity-dmips-mhz = <LIT_CAPACITY>;
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#elif TARGET_PLATFORM == 3
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clocks = <&scmi_dvfs 1>;
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capacity-dmips-mhz = <MID_CAPACITY>;
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#endif /* TARGET_PLATFORM == 3 */
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amu = <&amu>;
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supports-mpmm;
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};
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CPU4:cpu@400 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x400>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 1>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <MID_CAPACITY>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU5:cpu@500 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x500>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 1>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <MID_CAPACITY>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU6:cpu@600 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x600>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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#if TARGET_PLATFORM <= 2
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clocks = <&scmi_dvfs 1>;
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capacity-dmips-mhz = <MID_CAPACITY>;
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#elif TARGET_PLATFORM == 3
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clocks = <&scmi_dvfs 2>;
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capacity-dmips-mhz = <BIG_CAPACITY>;
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#endif /* TARGET_PLATFORM == 3 */
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amu = <&amu>;
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supports-mpmm;
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};
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CPU7:cpu@700 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x700>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
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clocks = <&scmi_dvfs 1>;
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capacity-dmips-mhz = <MID_CAPACITY>;
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#else
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clocks = <&scmi_dvfs 2>;
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capacity-dmips-mhz = <BIG_CAPACITY>;
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#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
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amu = <&amu>;
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supports-mpmm;
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};
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#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
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CPU8:cpu@800 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x800>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 1>;
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capacity-dmips-mhz = <MID_CAPACITY>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU9:cpu@900 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x900>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 2>;
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capacity-dmips-mhz = <BIG2_CAPACITY>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU10:cpu@A00 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0xA00>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 2>;
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capacity-dmips-mhz = <BIG2_CAPACITY>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU11:cpu@B00 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0xB00>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 2>;
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capacity-dmips-mhz = <BIG2_CAPACITY>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU12:cpu@C00 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0xC00>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 3>;
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capacity-dmips-mhz = <BIG_CAPACITY>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU13:cpu@D00 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0xD00>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 3>;
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capacity-dmips-mhz = <BIG_CAPACITY>;
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amu = <&amu>;
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supports-mpmm;
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};
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#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0x8000000>;
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linux,cma-default;
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};
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optee@f8e00000 {
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compatible = "restricted-dma-pool";
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reg = <0x00000000 0xf8e00000 0 0x00200000>;
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};
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fwu_mm@fca00000 {
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reg = <0x00000000 0xfca00000 0 0x00400000>;
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no-map;
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};
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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method = "smc";
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};
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cpu-pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
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<&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>
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#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
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,<&CPU8>, <&CPU9>, <&CPU10>, <&CPU11>,
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<&CPU12>, <&CPU13>
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#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
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;
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};
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sram: sram@6000000 {
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compatible = "mmio-sram";
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reg = <0x0 0x06000000 0x0 0x8000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0 0x06000000 0x8000>;
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cpu_scp_scmi_mem: scp-shmem@0 {
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compatible = "arm,scmi-shmem";
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reg = <0x0 0x80>;
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};
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};
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mbox_db_rx: mhu@MHU_RX_ADDR() {
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compatible = "arm,mhuv2-rx","arm,primecell";
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reg = <0x0 MHU_RX_ADDR(0x) 0x0 0x1000>;
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clocks = <&soc_refclk>;
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clock-names = "apb_pclk";
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#mbox-cells = <2>;
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interrupts = <GIC_SPI INT_MBOX_RX IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "mhu_rx";
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mhu-protocol = "doorbell";
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arm,mhuv2-protocols = <0 1>;
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};
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mbox_db_tx: mhu@MHU_TX_ADDR() {
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compatible = "arm,mhuv2-tx","arm,primecell";
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reg = <0x0 MHU_TX_ADDR(0x) 0x0 0x1000>;
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clocks = <&soc_refclk>;
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clock-names = "apb_pclk";
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#mbox-cells = <2>;
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interrupt-names = "mhu_tx";
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mhu-protocol = "doorbell";
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arm,mhuv2-protocols = <0 1>;
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};
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scmi {
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compatible = "arm,scmi";
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mbox-names = "tx", "rx";
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mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0 >;
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shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>;
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#address-cells = <1>;
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#size-cells = <0>;
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#if TC_SCMI_PD_CTRL_EN
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scmi_devpd: protocol@11 {
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reg = <0x11>;
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#power-domain-cells = <1>;
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};
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#endif /* TC_SCMI_PD_CTRL_EN */
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scmi_dvfs: protocol@13 {
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reg = <0x13>;
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#clock-cells = <1>;
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};
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scmi_clk: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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};
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};
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gic: interrupt-controller@GIC_CTRL_ADDR {
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compatible = "arm,gic-v3";
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#address-cells = <2>;
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#interrupt-cells = <3>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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reg = <0x0 0x30000000 0 0x10000>, /* GICD */
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<0x0 0x30080000 0 GIC_GICR_OFFSET>; /* GICR */
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interrupts = <GIC_PPI 0x9 IRQ_TYPE_LEVEL_LOW>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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soc_refclk: refclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <1000000000>;
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clock-output-names = "apb_pclk";
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};
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soc_refclk60mhz: refclk60mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <60000000>;
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clock-output-names = "iofpga_clk";
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};
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soc_uartclk: uartclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <UARTCLK_FREQ>;
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clock-output-names = "uartclk";
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};
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/* soc_uart0 on FPGA, ap_ns_uart on FVP */
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os_uart: serial@2a400000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0x2A400000 0x0 UART_OFFSET>;
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&soc_uartclk>, <&soc_refclk>;
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clock-names = "uartclk", "apb_pclk";
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status = "okay";
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};
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vencoder {
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compatible = "drm,virtual-encoder";
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port {
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vencoder_in: endpoint {
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remote-endpoint = <&dp_pl0_out0>;
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};
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};
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display-timings {
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timing-panel {
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VENCODER_TIMING;
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};
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};
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};
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ethernet@18000000 {
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compatible = ETH_COMPATIBLE;
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reg = <0x0 0x18000000 0x0 0x10000>;
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interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
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/* FPGA only but will work on FVP. Keep for simplicity */
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phy-mode = "mii";
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reg-io-width = <2>;
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smsc,irq-push-pull;
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};
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bp_clock24mhz: clock24mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "bp:clock24mhz";
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};
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sysreg: sysreg@1c010000 {
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compatible = "arm,vexpress-sysreg";
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reg = <0x0 0x001c010000 0x0 0x1000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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|
|
fixed_3v3: v2m-3v3 {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "3V3";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
mmci@1c050000 {
|
|
compatible = "arm,pl180", "arm,primecell";
|
|
reg = <0x0 0x001c050000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
MMC_REMOVABLE;
|
|
wp-gpios = <&sysreg 1 0>;
|
|
bus-width = <4>;
|
|
max-frequency = <25000000>;
|
|
vmmc-supply = <&fixed_3v3>;
|
|
clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
|
|
clock-names = "mclk", "apb_pclk";
|
|
};
|
|
|
|
gpu_clk: gpu_clk {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <1000000000>;
|
|
};
|
|
|
|
gpu_core_clk: gpu_core_clk {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <1000000000>;
|
|
};
|
|
|
|
gpu: gpu@2d000000 {
|
|
compatible = "arm,mali-midgard";
|
|
reg = <0x0 0x2d000000 0x0 0x200000>;
|
|
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "JOB", "MMU", "GPU";
|
|
clocks = <&gpu_core_clk>;
|
|
clock-names = "shadercores";
|
|
#if TC_SCMI_PD_CTRL_EN
|
|
power-domains = <&scmi_devpd GPU_SCMI_PD_IDX>;
|
|
scmi-perf-domain = <3>;
|
|
#endif /* TC_SCMI_PD_CTRL_EN */
|
|
|
|
#if TC_IOMMU_EN
|
|
iommus = <&smmu_700 0x200>;
|
|
#endif /* TC_IOMMU_EN */
|
|
};
|
|
|
|
power_model_simple {
|
|
/*
|
|
* Numbers used are irrelevant to Titan,
|
|
* it helps suppressing the kernel warnings.
|
|
*/
|
|
compatible = "arm,mali-simple-power-model";
|
|
static-coefficient = <2427750>;
|
|
dynamic-coefficient = <4687>;
|
|
ts = <20000 2000 (-20) 2>;
|
|
thermal-zone = "";
|
|
};
|
|
|
|
#if TC_IOMMU_EN
|
|
smmu_700: iommu@3f000000 {
|
|
#iommu-cells = <1>;
|
|
compatible = "arm,smmu-v3";
|
|
reg = <0x0 0x3f000000 0x0 0x5000000>;
|
|
interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 230 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "eventq", "cmdq-sync", "gerror";
|
|
dma-coherent;
|
|
};
|
|
#endif /* TC_IOMMU_EN */
|
|
|
|
dp0: display@2cc00000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "arm,mali-d71";
|
|
reg = <0 0x2cc00000 0 0x20000>;
|
|
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "DPU";
|
|
DPU_CLK_ATTR1;
|
|
#if TC_IOMMU_EN
|
|
iommus = <&smmu_700 0x100>;
|
|
#endif /* TC_IOMMU_EN */
|
|
#if TC_SCMI_PD_CTRL_EN && (TARGET_PLATFORM != 3)
|
|
power-domains = <&scmi_devpd DPU_SCMI_PD_IDX>;
|
|
#endif /* TC_SCMI_PD_CTRL_EN && (TARGET_PLATFORM != 3) */
|
|
|
|
pl0: pipeline@0 {
|
|
reg = <0>;
|
|
DPU_CLK_ATTR2;
|
|
pl_id = <0>;
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
port@0 {
|
|
reg = <0>;
|
|
dp_pl0_out0: endpoint {
|
|
remote-endpoint = <&vencoder_in>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
pl1: pipeline@1 {
|
|
reg = <1>;
|
|
DPU_CLK_ATTR3;
|
|
pl_id = <1>;
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
port@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
/*
|
|
* L3 cache in the DSU is the Memory System Component (MSC)
|
|
* The MPAM registers are accessed through utility bus in the DSU
|
|
*/
|
|
msc0 {
|
|
compatible = "arm,mpam-msc";
|
|
reg = <MPAM_ADDR 0x0 0x2000>;
|
|
};
|
|
|
|
ete0 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <&CPU0>;
|
|
};
|
|
|
|
ete1 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <&CPU1>;
|
|
};
|
|
|
|
ete2 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <&CPU2>;
|
|
};
|
|
|
|
ete3 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <&CPU3>;
|
|
};
|
|
|
|
ete4 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <&CPU4>;
|
|
};
|
|
|
|
ete5 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <&CPU5>;
|
|
};
|
|
|
|
ete6 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <&CPU6>;
|
|
};
|
|
|
|
ete7 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <&CPU7>;
|
|
};
|
|
|
|
#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
|
|
ete8 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <&CPU8>;
|
|
};
|
|
|
|
ete9 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <&CPU9>;
|
|
};
|
|
|
|
ete10 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <&CPU10>;
|
|
};
|
|
|
|
ete11 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <&CPU11>;
|
|
};
|
|
|
|
ete12 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <&CPU12>;
|
|
};
|
|
|
|
ete13 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <&CPU13>;
|
|
};
|
|
#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
|
|
|
|
trbe {
|
|
compatible = "arm,trace-buffer-extension";
|
|
interrupts = <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
trusty {
|
|
#size-cells = <0x02>;
|
|
#address-cells = <0x02>;
|
|
ranges = <0x00>;
|
|
compatible = "android,trusty-v1";
|
|
|
|
virtio {
|
|
compatible = "android,trusty-virtio-v1";
|
|
};
|
|
|
|
test {
|
|
compatible = "android,trusty-test-v1";
|
|
};
|
|
|
|
log {
|
|
compatible = "android,trusty-log-v1";
|
|
};
|
|
|
|
irq {
|
|
ipi-range = <0x08 0x0f 0x08>;
|
|
interrupt-ranges = <0x00 0x0f 0x00 0x10 0x1f 0x01 0x20 0x3f 0x02>;
|
|
interrupt-templates = <0x01 0x00 0x8001 0x01 0x01 0x04 0x8001 0x01 0x00 0x04>;
|
|
compatible = "android,trusty-irq-v1";
|
|
};
|
|
};
|
|
};
|