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a64bcc2b45
Cortex-A710 erratum 2081180 is a Cat B erratum present in r0p0, r1p0, and r2p0 of the Cortex-A710 processor core, and it is still open. A710 SDEN: https://developer.arm.com/documentation/SDEN1775101/1000 Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com> Change-Id: I1e8c2bc3d8dc326947ccfd91daf9083d666b2542
192 lines
4.5 KiB
ArmAsm
192 lines
4.5 KiB
ArmAsm
/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_a710.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex A710 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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/* --------------------------------------------------
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* Errata Workaround for Cortex-A710 Erratum 1987031.
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* This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710. It is still
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* open.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a710_1987031_wa
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/* Check revision. */
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mov x17, x30
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bl check_errata_1987031
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cbz x0, 1f
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/* Apply instruction patching sequence */
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ldr x0,=0x6
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msr S3_6_c15_c8_0,x0
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ldr x0,=0xF3A08002
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msr S3_6_c15_c8_2,x0
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ldr x0,=0xFFF0F7FE
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msr S3_6_c15_c8_3,x0
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ldr x0,=0x40000001003ff
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msr S3_6_c15_c8_1,x0
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ldr x0,=0x7
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msr S3_6_c15_c8_0,x0
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ldr x0,=0xBF200000
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msr S3_6_c15_c8_2,x0
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ldr x0,=0xFFEF0000
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msr S3_6_c15_c8_3,x0
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ldr x0,=0x40000001003f3
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msr S3_6_c15_c8_1,x0
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isb
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1:
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ret x17
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endfunc errata_a710_1987031_wa
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func check_errata_1987031
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/* Applies to r0p0, r1p0 and r2p0 */
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mov x1, #0x20
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b cpu_rev_var_ls
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endfunc check_errata_1987031
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/* --------------------------------------------------
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* Errata Workaround for Cortex-A710 Erratum 2081180.
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* This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710.
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* It is still open.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a710_2081180_wa
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/* Check revision. */
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mov x17, x30
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bl check_errata_2081180
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cbz x0, 1f
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/* Apply instruction patching sequence */
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ldr x0,=0x3
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msr S3_6_c15_c8_0,x0
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ldr x0,=0xF3A08002
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msr S3_6_c15_c8_2,x0
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ldr x0,=0xFFF0F7FE
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msr S3_6_c15_c8_3,x0
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ldr x0,=0x10002001003FF
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msr S3_6_c15_c8_1,x0
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ldr x0,=0x4
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msr S3_6_c15_c8_0,x0
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ldr x0,=0xBF200000
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msr S3_6_c15_c8_2,x0
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ldr x0,=0xFFEF0000
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msr S3_6_c15_c8_3,x0
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ldr x0,=0x10002001003F3
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msr S3_6_c15_c8_1,x0
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isb
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1:
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ret x17
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endfunc errata_a710_2081180_wa
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func check_errata_2081180
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/* Applies to r0p0, r1p0 and r2p0 */
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mov x1, #0x20
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b cpu_rev_var_ls
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endfunc check_errata_2081180
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func cortex_a710_core_pwr_dwn
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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mrs x0, CORTEX_A710_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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msr CORTEX_A710_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_a710_core_pwr_dwn
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/*
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* Errata printing function for Cortex A710. Must follow AAPCS.
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*/
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#if REPORT_ERRATA
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func cortex_a710_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_A710_1987031, cortex_a710, 1987031
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report_errata ERRATA_A710_2081180, cortex_a710, 2081180
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_a710_errata_report
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#endif
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func cortex_a710_reset_func
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mov x19, x30
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/* Disable speculative loads */
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msr SSBS, xzr
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bl cpu_get_rev_var
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mov x18, x0
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#if ERRATA_A710_1987031
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mov x0, x18
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bl errata_a710_1987031_wa
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#endif
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#if ERRATA_A710_2081180
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mov x0, x18
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bl errata_a710_2081180_wa
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#endif
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isb
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ret x19
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endfunc cortex_a710_reset_func
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/* ---------------------------------------------
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* This function provides Cortex-A710 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a710_regs, "aS"
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cortex_a710_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a710_cpu_reg_dump
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adr x6, cortex_a710_regs
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mrs x8, CORTEX_A710_CPUECTLR_EL1
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ret
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endfunc cortex_a710_cpu_reg_dump
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declare_cpu_ops cortex_a710, CORTEX_A710_MIDR, \
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cortex_a710_reset_func, \
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cortex_a710_core_pwr_dwn
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