mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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31137e1b15
Disable the debug flag from the driver to reduce debugging messages. Change-Id: I9444f64acbf684debab56d8226b14c6c01200ea4 Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>
144 lines
7 KiB
C
144 lines
7 KiB
C
/*
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* Copyright (c) 2024, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef APUSYS_DEVAPC_DEF_H
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#define APUSYS_DEVAPC_DEF_H
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#include <lib/mmio.h>
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#include <devapc/apusys_dapc_v1.h>
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/* Control */
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#define SLAVE_RCX_BULK0 SLAVE_FORBID_EXCEPT_D0_D11_NO_PROTECT_D3_D5_D8_SEC_RW
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#define SLAVE_RCX_BULK1 SLAVE_FORBID_EXCEPT_D0_NO_PROTECT_D5_D8_SEC_RW
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#define SLAVE_MD32_APB SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D3_D5_SEC_RW
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#define SLAVE_ACP_TCU_SSC SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_VCORE SLAVE_FORBID_EXCEPT_D0_NO_PROTECT_D3_D5_SEC_RW
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#define SLAVE_WDEC SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW
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#define SLAVE_SMMU_IP_REG SLAVE_FORBID_EXCEPT_D3_D5_SEC_RW_D0_D4_D11_NO_PROTECT
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#define SLAVE_SMMU_NSEC SLAVE_FORBID_EXCEPT_D5_SEC_RW_D0_NO_PROTECT
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#define SLAVE_SMMU_SEC SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW
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#define SLAVE_RPC SLAVE_FORBID_EXCEPT_D3_D5_SEC_RW_D0_D11_NO_PROTECT
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#define SLAVE_PCU SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D3_D5_SEC_RW
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#define SLAVE_AO_CTRL SLAVE_FORBID_EXCEPT_D0_D3_D5_SEC_RW
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#define SLAVE_ACC SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D3_D5_SEC_RW
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#define SLAVE_PLL SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_D8_SEC_RW
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#define SLAVE_SEC SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW
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#define SLAVE_ARE0 SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_SEC_RW
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#define SLAVE_ARE1 SLAVE_FORBID_EXCEPT_D0_D11_NO_PROTECT_D3_D5_D8_SEC_RW
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#define SLAVE_RPC_MDLA SLAVE_FORBID_EXCEPT_D5_D8_SEC_RW
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#define SLAVE_MDLA_DBG SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_TOP_PMU SLAVE_FORBID_EXCEPT_D5_D8_SEC_RW
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#define SLAVE_UNDEFINE0 SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_UNDEFINE1 SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_UNDEFINE2 SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_UNDEFINE3 SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_UNDEFINE4 SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_UNDEFINE5 SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_UNDEFINE6 SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_UNDEFINE7 SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_UNDEFINE8 SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_UNDEFINE9 SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_UNDEFINE10 SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_DATA_BULK SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW
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#define SLAVE_AO_BCRM SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_AO_DAPC_WRAP SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_AO_DAPC_CON SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW
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#define SLAVE_ACX0_AO SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_SEC_RW
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#define SLAVE_ACX0_BULK SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_SEC_RW
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#define SLAVE_ACX0_RPC SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_SEC_RW
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#define SLAVE_ACX0_AO_CTRL SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_ACX1_AO SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_SEC_RW
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#define SLAVE_ACX1_BULK SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_SEC_RW
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#define SLAVE_ACX1_RPC SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_SEC_RW
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#define SLAVE_ACX1_AO_CTRL SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_NCX_AO SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_SEC_RW
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#define SLAVE_NCX_BULK SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_SEC_RW
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#define SLAVE_NCX_RPC SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_NCX_AO_CTRL SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_MD32_SYSCTRL SLAVE_FORBID_EXCEPT_D0_D3_D5_SEC_RW
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#define SLAVE_MD32_PMU SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D3_D5_SEC_RW
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#define SLAVE_LOG_TOP0 SLAVE_FORBID_EXCEPT_D0_D5_D7_D14_NO_PROTECT
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#define SLAVE_LOG_TOP1 SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_RCX_CFG SLAVE_FORBID_EXCEPT_D0_NO_PROTECT_D3_D5_SEC_RW
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#define SLAVE_ACX_IPS SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_RCX_TCU0 SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW
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#define SLAVE_RCX_TCU1 SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW
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#define SLAVE_RCX_TCU2 SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_RCX_TCU3 SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_RCX_TCU4 SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_RCX_TCU5 SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_RCX_TCU6 SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_RCX_NOC_CFG SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW
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#define SLAVE_MDLA_CORE_CTRL SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW
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#define SLAVE_MDLA_BIU SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_MDLA_PMU SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_MDLA_CMDE SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW
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#define SLAVE_EDPA0 SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_EDPA1 SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_RCX_CMU SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW
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#define SLAVE_RCX_ACS SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW
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#define SLAVE_MD32_WDT SLAVE_FORBID_EXCEPT_D0_D3_D5_SEC_RW
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#define SLAVE_MD32_CACHE SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW
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#define SLAVE_MD32_DBG SLAVE_FORBID_EXCEPT_D0_NO_PROTECT_D5_SEC_RW
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#define SLAVE_INFRA_DBG SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW
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#define SLAVE_IOMMU0_BANK0 SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_IOMMU0_BANK1 SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_IOMMU0_BANK2 SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_IOMMU0_BANK3 SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_IOMMU0_BANK4 SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_IOMMU1_BANK0 SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_IOMMU1_BANK1 SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_IOMMU1_BANK2 SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_IOMMU1_BANK3 SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_IOMMU1_BANK4 SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_S0_SSC SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_N0_SSC SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_ACP_SSC SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_S1_SSC SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_N1_SSC SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_SEMA_STIMER SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_EMI_CFG SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_CPE_SENSOR SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_CPE_COEF SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_CPE_CTRL SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_TPPA SLAVE_FORBID_EXCEPT_D5_D8_SEC_RW
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#define SLAVE_SENSOR_ACX0_DLA0 SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_SENSOR_ACX0_VPU SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_SENSOR_ACX1_DLA0 SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_SENSOR_ACX1_VPU SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_SENSOR_NCX_DLA0 SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_SENSOR_NCX_NVE SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_RCX_BCRM SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_RCX_DAPC_WRAP SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_RCX_DAPC_CON SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW
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#define SLAVE_HSE SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_RCX_CBFC SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#define SLAVE_SONC SLAVE_FORBID_EXCEPT_D0_D5_SEC_RW
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#define SLAVE_SCMDQ SLAVE_FORBID_EXCEPT_D5_SEC_RW
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#if DEBUG
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#define SLAVE_PTP_THM SLAVE_FORBID_EXCEPT_D0_NO_PROTECT_D5_SEC_RW
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#else
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#define SLAVE_PTP_THM SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_SEC_RW
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#endif
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/* Power Domain: AO */
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#define APUSYS_CTRL_DAPC_AO_SLAVE_NUM_IN_1_DOM (16)
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#define APUSYS_CTRL_DAPC_AO_DOM_NUM (16)
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#define APUSYS_CTRL_DAPC_AO_SLAVE_NUM (67) /* 0~66 */
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#define DEVAPC_MASK (0x3U)
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#define DEVAPC_DOM_SHIFT (2)
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/* Power Domain: RCX */
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#define APUSYS_CTRL_DAPC_RCX_SLAVE_NUM_IN_1_DOM (16)
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#define APUSYS_CTRL_DAPC_RCX_DOM_NUM (16)
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#define APUSYS_CTRL_DAPC_RCX_SLAVE_NUM (95) /* 0~94 */
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/* Dump Config */
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#undef DUMP_CFG
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#endif
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