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https://github.com/ARM-software/arm-trusted-firmware.git
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1e9428ea96
Add helper function gicv3_get_spi_limit() to get the value of (maximum SPI INTID + 1), so that some duplicated code can be removed later. Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com> Change-Id: I160c8a88fbb71d22790b8999a84afbfba766f5e7
706 lines
21 KiB
C
706 lines
21 KiB
C
/*
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* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef GICV3_PRIVATE_H
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#define GICV3_PRIVATE_H
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#include <assert.h>
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#include <stdint.h>
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#include <drivers/arm/gic_common.h>
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#include <drivers/arm/gicv3.h>
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#include <lib/mmio.h>
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#include "../common/gic_common_private.h"
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/*******************************************************************************
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* GICv3 private macro definitions
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******************************************************************************/
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/* Constants to indicate the status of the RWP bit */
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#define RWP_TRUE U(1)
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#define RWP_FALSE U(0)
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/* Calculate GIC register bit number corresponding to its interrupt ID */
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#define BIT_NUM(REG, id) \
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((id) & ((1U << REG##R_SHIFT) - 1U))
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/*
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* Calculate 8, 32 and 64-bit GICD register offset
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* corresponding to its interrupt ID
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*/
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#if GIC_EXT_INTID
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/* GICv3.1 */
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#define GICD_OFFSET_8(REG, id) \
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(((id) <= MAX_SPI_ID) ? \
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GICD_##REG##R + (uintptr_t)(id) : \
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GICD_##REG##RE + (uintptr_t)(id) - MIN_ESPI_ID)
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#define GICD_OFFSET(REG, id) \
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(((id) <= MAX_SPI_ID) ? \
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GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2) : \
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GICD_##REG##RE + ((((uintptr_t)(id) - MIN_ESPI_ID) >> \
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REG##R_SHIFT) << 2))
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#define GICD_OFFSET_64(REG, id) \
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(((id) <= MAX_SPI_ID) ? \
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GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 3) : \
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GICD_##REG##RE + ((((uintptr_t)(id) - MIN_ESPI_ID) >> \
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REG##R_SHIFT) << 3))
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#else /* GICv3 */
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#define GICD_OFFSET_8(REG, id) \
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(GICD_##REG##R + (uintptr_t)(id))
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#define GICD_OFFSET(REG, id) \
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(GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2))
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#define GICD_OFFSET_64(REG, id) \
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(GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 3))
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#endif /* GIC_EXT_INTID */
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/*
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* Read/Write 8, 32 and 64-bit GIC Distributor register
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* corresponding to its interrupt ID
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*/
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#define GICD_READ(REG, base, id) \
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mmio_read_32((base) + GICD_OFFSET(REG, (id)))
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#define GICD_READ_64(REG, base, id) \
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mmio_read_64((base) + GICD_OFFSET_64(REG, (id)))
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#define GICD_WRITE_8(REG, base, id, val) \
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mmio_write_8((base) + GICD_OFFSET_8(REG, (id)), (val))
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#define GICD_WRITE(REG, base, id, val) \
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mmio_write_32((base) + GICD_OFFSET(REG, (id)), (val))
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#define GICD_WRITE_64(REG, base, id, val) \
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mmio_write_64((base) + GICD_OFFSET_64(REG, (id)), (val))
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/*
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* Bit operations on GIC Distributor register corresponding
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* to its interrupt ID
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*/
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/* Get bit in GIC Distributor register */
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#define GICD_GET_BIT(REG, base, id) \
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((mmio_read_32((base) + GICD_OFFSET(REG, (id))) >> \
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BIT_NUM(REG, (id))) & 1U)
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/* Set bit in GIC Distributor register */
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#define GICD_SET_BIT(REG, base, id) \
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mmio_setbits_32((base) + GICD_OFFSET(REG, (id)), \
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((uint32_t)1 << BIT_NUM(REG, (id))))
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/* Clear bit in GIC Distributor register */
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#define GICD_CLR_BIT(REG, base, id) \
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mmio_clrbits_32((base) + GICD_OFFSET(REG, (id)), \
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((uint32_t)1 << BIT_NUM(REG, (id))))
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/* Write bit in GIC Distributor register */
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#define GICD_WRITE_BIT(REG, base, id) \
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mmio_write_32((base) + GICD_OFFSET(REG, (id)), \
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((uint32_t)1 << BIT_NUM(REG, (id))))
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/*
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* Calculate 8 and 32-bit GICR register offset
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* corresponding to its interrupt ID
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*/
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#if GIC_EXT_INTID
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/* GICv3.1 */
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#define GICR_OFFSET_8(REG, id) \
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(((id) <= MAX_PPI_ID) ? \
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GICR_##REG##R + (uintptr_t)(id) : \
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GICR_##REG##R + (uintptr_t)(id) - (MIN_EPPI_ID - MIN_SPI_ID))
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#define GICR_OFFSET(REG, id) \
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(((id) <= MAX_PPI_ID) ? \
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GICR_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2) : \
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GICR_##REG##R + ((((uintptr_t)(id) - (MIN_EPPI_ID - MIN_SPI_ID))\
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>> REG##R_SHIFT) << 2))
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#else /* GICv3 */
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#define GICR_OFFSET_8(REG, id) \
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(GICR_##REG##R + (uintptr_t)(id))
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#define GICR_OFFSET(REG, id) \
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(GICR_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2))
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#endif /* GIC_EXT_INTID */
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/* Read/Write GIC Redistributor register corresponding to its interrupt ID */
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#define GICR_READ(REG, base, id) \
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mmio_read_32((base) + GICR_OFFSET(REG, (id)))
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#define GICR_WRITE_8(REG, base, id, val) \
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mmio_write_8((base) + GICR_OFFSET_8(REG, (id)), (val))
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#define GICR_WRITE(REG, base, id, val) \
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mmio_write_32((base) + GICR_OFFSET(REG, (id)), (val))
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/*
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* Bit operations on GIC Redistributor register
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* corresponding to its interrupt ID
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*/
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/* Get bit in GIC Redistributor register */
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#define GICR_GET_BIT(REG, base, id) \
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((mmio_read_32((base) + GICR_OFFSET(REG, (id))) >> \
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BIT_NUM(REG, (id))) & 1U)
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/* Write bit in GIC Redistributor register */
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#define GICR_WRITE_BIT(REG, base, id) \
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mmio_write_32((base) + GICR_OFFSET(REG, (id)), \
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((uint32_t)1 << BIT_NUM(REG, (id))))
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/* Set bit in GIC Redistributor register */
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#define GICR_SET_BIT(REG, base, id) \
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mmio_setbits_32((base) + GICR_OFFSET(REG, (id)), \
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((uint32_t)1 << BIT_NUM(REG, (id))))
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/* Clear bit in GIC Redistributor register */
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#define GICR_CLR_BIT(REG, base, id) \
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mmio_clrbits_32((base) + GICR_OFFSET(REG, (id)), \
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((uint32_t)1 << BIT_NUM(REG, (id))))
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/*
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* Macro to convert an mpidr to a value suitable for programming into a
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* GICD_IROUTER. Bits[31:24] in the MPIDR are cleared as they are not relevant
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* to GICv3.
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*/
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static inline u_register_t gicd_irouter_val_from_mpidr(u_register_t mpidr,
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unsigned int irm)
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{
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return (mpidr & ~(U(0xff) << 24)) |
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((irm & IROUTER_IRM_MASK) << IROUTER_IRM_SHIFT);
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}
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/*
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* Macro to convert a GICR_TYPER affinity value into a MPIDR value. Bits[31:24]
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* are zeroes.
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*/
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#ifdef __aarch64__
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static inline u_register_t mpidr_from_gicr_typer(uint64_t typer_val)
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{
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return (((typer_val >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) |
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((typer_val >> 32) & U(0xffffff));
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}
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#else
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static inline u_register_t mpidr_from_gicr_typer(uint64_t typer_val)
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{
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return (((typer_val) >> 32) & U(0xffffff));
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}
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#endif
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/*******************************************************************************
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* GICv3 private global variables declarations
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******************************************************************************/
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extern const gicv3_driver_data_t *gicv3_driver_data;
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/*******************************************************************************
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* Private GICv3 function prototypes for accessing entire registers.
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* Note: The raw register values correspond to multiple interrupt IDs and
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* the number of interrupt IDs involved depends on the register accessed.
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******************************************************************************/
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unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id);
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unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id);
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void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val);
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void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val);
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/*******************************************************************************
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* Private GICv3 function prototypes for accessing the GIC registers
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* corresponding to a single interrupt ID. These functions use bitwise
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* operations or appropriate register accesses to modify or return
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* the bit-field corresponding the single interrupt ID.
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******************************************************************************/
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unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id);
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unsigned int gicr_get_igrpmodr(uintptr_t base, unsigned int id);
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unsigned int gicr_get_igroupr(uintptr_t base, unsigned int id);
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unsigned int gicr_get_isactiver(uintptr_t base, unsigned int id);
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void gicd_set_igrpmodr(uintptr_t base, unsigned int id);
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void gicr_set_igrpmodr(uintptr_t base, unsigned int id);
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void gicr_set_isenabler(uintptr_t base, unsigned int id);
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void gicr_set_icenabler(uintptr_t base, unsigned int id);
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void gicr_set_ispendr(uintptr_t base, unsigned int id);
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void gicr_set_icpendr(uintptr_t base, unsigned int id);
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void gicr_set_igroupr(uintptr_t base, unsigned int id);
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void gicd_clr_igrpmodr(uintptr_t base, unsigned int id);
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void gicr_clr_igrpmodr(uintptr_t base, unsigned int id);
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void gicr_clr_igroupr(uintptr_t base, unsigned int id);
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void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri);
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void gicr_set_icfgr(uintptr_t base, unsigned int id, unsigned int cfg);
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/*******************************************************************************
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* Private GICv3 helper function prototypes
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******************************************************************************/
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unsigned int gicv3_get_spi_limit(uintptr_t gicd_base);
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void gicv3_spis_config_defaults(uintptr_t gicd_base);
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void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base);
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unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base,
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const interrupt_prop_t *interrupt_props,
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unsigned int interrupt_props_num);
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unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base,
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const interrupt_prop_t *interrupt_props,
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unsigned int interrupt_props_num);
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void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs,
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unsigned int rdistif_num,
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uintptr_t gicr_base,
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mpidr_hash_fn mpidr_to_core_pos);
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void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base);
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void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base);
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/*******************************************************************************
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* GIC Distributor interface accessors
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******************************************************************************/
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/*
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* Wait for updates to:
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* GICD_CTLR[2:0] - the Group Enables
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* GICD_CTLR[7:4] - the ARE bits, E1NWF bit and DS bit
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* GICD_ICENABLER<n> - the clearing of enable state for SPIs
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*/
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static inline void gicd_wait_for_pending_write(uintptr_t gicd_base)
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{
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while ((gicd_read_ctlr(gicd_base) & GICD_CTLR_RWP_BIT) != 0U) {
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}
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}
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static inline uint32_t gicd_read_pidr2(uintptr_t base)
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{
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return mmio_read_32(base + GICD_PIDR2_GICV3);
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}
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static inline uint64_t gicd_read_irouter(uintptr_t base, unsigned int id)
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{
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assert(id >= MIN_SPI_ID);
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return GICD_READ_64(IROUTE, base, id);
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}
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static inline void gicd_write_irouter(uintptr_t base,
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unsigned int id,
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uint64_t affinity)
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{
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assert(id >= MIN_SPI_ID);
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GICD_WRITE_64(IROUTE, base, id, affinity);
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}
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static inline void gicd_clr_ctlr(uintptr_t base,
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unsigned int bitmap,
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unsigned int rwp)
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{
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gicd_write_ctlr(base, gicd_read_ctlr(base) & ~bitmap);
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if (rwp != 0U) {
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gicd_wait_for_pending_write(base);
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}
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}
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static inline void gicd_set_ctlr(uintptr_t base,
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unsigned int bitmap,
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unsigned int rwp)
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{
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gicd_write_ctlr(base, gicd_read_ctlr(base) | bitmap);
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if (rwp != 0U) {
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gicd_wait_for_pending_write(base);
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}
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}
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/*******************************************************************************
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* GIC Redistributor interface accessors
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******************************************************************************/
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static inline uint32_t gicr_read_ctlr(uintptr_t base)
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{
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return mmio_read_32(base + GICR_CTLR);
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}
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static inline void gicr_write_ctlr(uintptr_t base, uint32_t val)
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{
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mmio_write_32(base + GICR_CTLR, val);
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}
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static inline uint64_t gicr_read_typer(uintptr_t base)
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{
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return mmio_read_64(base + GICR_TYPER);
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}
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static inline uint32_t gicr_read_waker(uintptr_t base)
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{
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return mmio_read_32(base + GICR_WAKER);
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}
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static inline void gicr_write_waker(uintptr_t base, uint32_t val)
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{
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mmio_write_32(base + GICR_WAKER, val);
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}
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/*
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* Wait for updates to:
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* GICR_ICENABLER0
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* GICR_CTLR.DPG1S
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* GICR_CTLR.DPG1NS
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* GICR_CTLR.DPG0
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* GICR_CTLR, which clears EnableLPIs from 1 to 0
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*/
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static inline void gicr_wait_for_pending_write(uintptr_t gicr_base)
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{
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while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT) != 0U) {
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}
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}
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static inline void gicr_wait_for_upstream_pending_write(uintptr_t gicr_base)
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{
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while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_UWP_BIT) != 0U) {
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}
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}
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/* Private implementation of Distributor power control hooks */
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void arm_gicv3_distif_pre_save(unsigned int rdist_proc_num);
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void arm_gicv3_distif_post_restore(unsigned int rdist_proc_num);
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/*******************************************************************************
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* GIC Redistributor functions for accessing entire registers.
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* Note: The raw register values correspond to multiple interrupt IDs and
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* the number of interrupt IDs involved depends on the register accessed.
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******************************************************************************/
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/*
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* Accessors to read/write GIC Redistributor ICENABLER0 register
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*/
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static inline unsigned int gicr_read_icenabler0(uintptr_t base)
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{
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return mmio_read_32(base + GICR_ICENABLER0);
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}
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static inline void gicr_write_icenabler0(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICR_ICENABLER0, val);
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}
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/*
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* Accessors to read/write GIC Redistributor ICENABLER0 and ICENABLERE
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* register corresponding to its number
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*/
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static inline unsigned int gicr_read_icenabler(uintptr_t base,
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unsigned int reg_num)
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{
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return mmio_read_32(base + GICR_ICENABLER + (reg_num << 2));
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}
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static inline void gicr_write_icenabler(uintptr_t base, unsigned int reg_num,
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unsigned int val)
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{
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mmio_write_32(base + GICR_ICENABLER + (reg_num << 2), val);
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}
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/*
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* Accessors to read/write GIC Redistributor ICFGR0, ICFGR1 registers
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*/
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static inline unsigned int gicr_read_icfgr0(uintptr_t base)
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{
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return mmio_read_32(base + GICR_ICFGR0);
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}
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static inline unsigned int gicr_read_icfgr1(uintptr_t base)
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{
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return mmio_read_32(base + GICR_ICFGR1);
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}
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static inline void gicr_write_icfgr0(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICR_ICFGR0, val);
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}
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static inline void gicr_write_icfgr1(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICR_ICFGR1, val);
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}
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/*
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* Accessors to read/write GIC Redistributor ICFGR0, ICFGR1 and ICFGRE
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* register corresponding to its number
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*/
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static inline unsigned int gicr_read_icfgr(uintptr_t base, unsigned int reg_num)
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{
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return mmio_read_32(base + GICR_ICFGR + (reg_num << 2));
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}
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static inline void gicr_write_icfgr(uintptr_t base, unsigned int reg_num,
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unsigned int val)
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{
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mmio_write_32(base + GICR_ICFGR + (reg_num << 2), val);
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}
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/*
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* Accessor to write GIC Redistributor ICPENDR0 register
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*/
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static inline void gicr_write_icpendr0(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICR_ICPENDR0, val);
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}
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/*
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* Accessor to write GIC Redistributor ICPENDR0 and ICPENDRE
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* register corresponding to its number
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*/
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static inline void gicr_write_icpendr(uintptr_t base, unsigned int reg_num,
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unsigned int val)
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{
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mmio_write_32(base + GICR_ICPENDR + (reg_num << 2), val);
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}
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/*
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* Accessors to read/write GIC Redistributor IGROUPR0 register
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*/
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static inline unsigned int gicr_read_igroupr0(uintptr_t base)
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{
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return mmio_read_32(base + GICR_IGROUPR0);
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}
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static inline void gicr_write_igroupr0(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICR_IGROUPR0, val);
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}
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/*
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* Accessors to read/write GIC Redistributor IGROUPR0 and IGROUPRE
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* register corresponding to its number
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*/
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static inline unsigned int gicr_read_igroupr(uintptr_t base,
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unsigned int reg_num)
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{
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return mmio_read_32(base + GICR_IGROUPR + (reg_num << 2));
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}
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static inline void gicr_write_igroupr(uintptr_t base, unsigned int reg_num,
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unsigned int val)
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{
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mmio_write_32(base + GICR_IGROUPR + (reg_num << 2), val);
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}
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/*
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* Accessors to read/write GIC Redistributor IGRPMODR0 register
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*/
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static inline unsigned int gicr_read_igrpmodr0(uintptr_t base)
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{
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return mmio_read_32(base + GICR_IGRPMODR0);
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}
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static inline void gicr_write_igrpmodr0(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICR_IGRPMODR0, val);
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}
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/*
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* Accessors to read/write GIC Redistributor IGRPMODR0 and IGRPMODRE
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* register corresponding to its number
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*/
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static inline unsigned int gicr_read_igrpmodr(uintptr_t base,
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unsigned int reg_num)
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{
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return mmio_read_32(base + GICR_IGRPMODR + (reg_num << 2));
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}
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static inline void gicr_write_igrpmodr(uintptr_t base, unsigned int reg_num,
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unsigned int val)
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{
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mmio_write_32(base + GICR_IGRPMODR + (reg_num << 2), val);
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}
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/*
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* Accessors to read/write the GIC Redistributor IPRIORITYR(E) register
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* corresponding to its number, 4 interrupts IDs at a time.
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*/
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static inline unsigned int gicr_ipriorityr_read(uintptr_t base,
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unsigned int reg_num)
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{
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return mmio_read_32(base + GICR_IPRIORITYR + (reg_num << 2));
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}
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static inline void gicr_ipriorityr_write(uintptr_t base, unsigned int reg_num,
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unsigned int val)
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{
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mmio_write_32(base + GICR_IPRIORITYR + (reg_num << 2), val);
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}
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/*
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* Accessors to read/write GIC Redistributor ISACTIVER0 register
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*/
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static inline unsigned int gicr_read_isactiver0(uintptr_t base)
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{
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return mmio_read_32(base + GICR_ISACTIVER0);
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}
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static inline void gicr_write_isactiver0(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICR_ISACTIVER0, val);
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}
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/*
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* Accessors to read/write GIC Redistributor ISACTIVER0 and ISACTIVERE
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* register corresponding to its number
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*/
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static inline unsigned int gicr_read_isactiver(uintptr_t base,
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unsigned int reg_num)
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{
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return mmio_read_32(base + GICR_ISACTIVER + (reg_num << 2));
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}
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static inline void gicr_write_isactiver(uintptr_t base, unsigned int reg_num,
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unsigned int val)
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{
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mmio_write_32(base + GICR_ISACTIVER + (reg_num << 2), val);
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}
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/*
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* Accessors to read/write GIC Redistributor ISENABLER0 register
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*/
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static inline unsigned int gicr_read_isenabler0(uintptr_t base)
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{
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return mmio_read_32(base + GICR_ISENABLER0);
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}
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static inline void gicr_write_isenabler0(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICR_ISENABLER0, val);
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}
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/*
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* Accessors to read/write GIC Redistributor ISENABLER0 and ISENABLERE
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* register corresponding to its number
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*/
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static inline unsigned int gicr_read_isenabler(uintptr_t base,
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unsigned int reg_num)
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{
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return mmio_read_32(base + GICR_ISENABLER + (reg_num << 2));
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}
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static inline void gicr_write_isenabler(uintptr_t base, unsigned int reg_num,
|
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unsigned int val)
|
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{
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mmio_write_32(base + GICR_ISENABLER + (reg_num << 2), val);
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}
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|
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/*
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* Accessors to read/write GIC Redistributor ISPENDR0 register
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*/
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static inline unsigned int gicr_read_ispendr0(uintptr_t base)
|
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{
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return mmio_read_32(base + GICR_ISPENDR0);
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}
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|
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static inline void gicr_write_ispendr0(uintptr_t base, unsigned int val)
|
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{
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mmio_write_32(base + GICR_ISPENDR0, val);
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}
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|
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/*
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* Accessors to read/write GIC Redistributor ISPENDR0 and ISPENDRE
|
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* register corresponding to its number
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*/
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static inline unsigned int gicr_read_ispendr(uintptr_t base,
|
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unsigned int reg_num)
|
|
{
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return mmio_read_32(base + GICR_ISPENDR + (reg_num << 2));
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}
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static inline void gicr_write_ispendr(uintptr_t base, unsigned int reg_num,
|
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unsigned int val)
|
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{
|
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mmio_write_32(base + GICR_ISPENDR + (reg_num << 2), val);
|
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}
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|
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/*
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* Accessors to read/write GIC Redistributor NSACR register
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*/
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static inline unsigned int gicr_read_nsacr(uintptr_t base)
|
|
{
|
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return mmio_read_32(base + GICR_NSACR);
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}
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static inline void gicr_write_nsacr(uintptr_t base, unsigned int val)
|
|
{
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mmio_write_32(base + GICR_NSACR, val);
|
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}
|
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|
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/*
|
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* Accessors to read/write GIC Redistributor PROPBASER register
|
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*/
|
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static inline uint64_t gicr_read_propbaser(uintptr_t base)
|
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{
|
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return mmio_read_64(base + GICR_PROPBASER);
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}
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static inline void gicr_write_propbaser(uintptr_t base, uint64_t val)
|
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{
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mmio_write_64(base + GICR_PROPBASER, val);
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}
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|
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/*
|
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* Accessors to read/write GIC Redistributor PENDBASER register
|
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*/
|
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static inline uint64_t gicr_read_pendbaser(uintptr_t base)
|
|
{
|
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return mmio_read_64(base + GICR_PENDBASER);
|
|
}
|
|
|
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static inline void gicr_write_pendbaser(uintptr_t base, uint64_t val)
|
|
{
|
|
mmio_write_64(base + GICR_PENDBASER, val);
|
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}
|
|
|
|
/*******************************************************************************
|
|
* GIC ITS functions to read and write entire ITS registers.
|
|
******************************************************************************/
|
|
static inline uint32_t gits_read_ctlr(uintptr_t base)
|
|
{
|
|
return mmio_read_32(base + GITS_CTLR);
|
|
}
|
|
|
|
static inline void gits_write_ctlr(uintptr_t base, uint32_t val)
|
|
{
|
|
mmio_write_32(base + GITS_CTLR, val);
|
|
}
|
|
|
|
static inline uint64_t gits_read_cbaser(uintptr_t base)
|
|
{
|
|
return mmio_read_64(base + GITS_CBASER);
|
|
}
|
|
|
|
static inline void gits_write_cbaser(uintptr_t base, uint64_t val)
|
|
{
|
|
mmio_write_64(base + GITS_CBASER, val);
|
|
}
|
|
|
|
static inline uint64_t gits_read_cwriter(uintptr_t base)
|
|
{
|
|
return mmio_read_64(base + GITS_CWRITER);
|
|
}
|
|
|
|
static inline void gits_write_cwriter(uintptr_t base, uint64_t val)
|
|
{
|
|
mmio_write_64(base + GITS_CWRITER, val);
|
|
}
|
|
|
|
static inline uint64_t gits_read_baser(uintptr_t base,
|
|
unsigned int its_table_id)
|
|
{
|
|
assert(its_table_id < 8U);
|
|
return mmio_read_64(base + GITS_BASER + (8U * its_table_id));
|
|
}
|
|
|
|
static inline void gits_write_baser(uintptr_t base, unsigned int its_table_id,
|
|
uint64_t val)
|
|
{
|
|
assert(its_table_id < 8U);
|
|
mmio_write_64(base + GITS_BASER + (8U * its_table_id), val);
|
|
}
|
|
|
|
/*
|
|
* Wait for Quiescent bit when GIC ITS is disabled
|
|
*/
|
|
static inline void gits_wait_for_quiescent_bit(uintptr_t gits_base)
|
|
{
|
|
assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U);
|
|
while ((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) == 0U) {
|
|
}
|
|
}
|
|
|
|
#endif /* GICV3_PRIVATE_H */
|