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https://github.com/ARM-software/arm-trusted-firmware.git
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a4668c36f1
Not tested on FVP Model. Change-Id: Iedebc5c1fbc7ea577e94142b7feafa5546f1f4f9 Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
100 lines
2.9 KiB
ArmAsm
100 lines
2.9 KiB
ArmAsm
/*
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* Copyright (c) 2019, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_hercules_ae.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "cortex_hercules_ae must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-Hercules-AE
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* -------------------------------------------------
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*/
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#if ENABLE_AMU
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func cortex_hercules_ae_reset_func
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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mrs x0, actlr_el3
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bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT
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msr actlr_el3, x0
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/* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */
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mrs x0, actlr_el2
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bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT
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msr actlr_el2, x0
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/* Enable group0 counters */
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mov x0, #CORTEX_HERCULES_AMU_GROUP0_MASK
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msr CPUAMCNTENSET0_EL0, x0
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/* Enable group1 counters */
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mov x0, #CORTEX_HERCULES_AMU_GROUP1_MASK
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msr CPUAMCNTENSET1_EL0, x0
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isb
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ret
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endfunc cortex_hercules_ae_reset_func
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#endif
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/* -------------------------------------------------------
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* HW will do the cache maintenance while powering down
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* -------------------------------------------------------
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*/
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func cortex_hercules_ae_core_pwr_dwn
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/* -------------------------------------------------------
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* Enable CPU power down bit in power control register
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* -------------------------------------------------------
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*/
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mrs x0, CORTEX_HERCULES_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_HERCULES_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
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msr CORTEX_HERCULES_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_hercules_ae_core_pwr_dwn
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/*
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* Errata printing function for cortex_hercules_ae. Must follow AAPCS.
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*/
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#if REPORT_ERRATA
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func cortex_hercules_ae_errata_report
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ret
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endfunc cortex_hercules_ae_errata_report
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#endif
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/* -------------------------------------------------------
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* This function provides cortex_hercules_ae specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* -------------------------------------------------------
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*/
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.section .rodata.cortex_hercules_ae_regs, "aS"
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cortex_hercules_ae_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_hercules_ae_cpu_reg_dump
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adr x6, cortex_hercules_ae_regs
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mrs x8, CORTEX_HERCULES_CPUECTLR_EL1
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ret
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endfunc cortex_hercules_ae_cpu_reg_dump
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#if ENABLE_AMU
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#define HERCULES_AE_RESET_FUNC cortex_hercules_ae_reset_func
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#else
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#define HERCULES_AE_RESET_FUNC CPU_NO_RESET_FUNC
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#endif
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declare_cpu_ops cortex_hercules_ae, CORTEX_HERCULES_AE_MIDR, \
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HERCULES_AE_RESET_FUNC, \
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cortex_hercules_ae_core_pwr_dwn
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