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https://github.com/ARM-software/arm-trusted-firmware.git
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f660533729
Many parts of the code were duplicating symbols that are defined in include/common/bl_common.h. It is better to only use the definitions in this header. As all the symbols refer to virtual addresses, they have to be uintptr_t, not unsigned long. This has also been fixed in bl_common.h. Change-Id: I204081af78326ced03fb05f69846f229d324c711 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
148 lines
4.3 KiB
C
148 lines
4.3 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <string.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <drivers/arm/gic_common.h>
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#include <drivers/arm/gicv2.h>
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#include <drivers/console.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables.h>
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#include <plat/common/platform.h>
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#include "../qemu_private.h"
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#if RESET_TO_SP_MIN
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#error qemu does not support RESET_TO_SP_MIN
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#endif
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static entry_point_info_t bl33_image_ep_info;
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/******************************************************************************
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* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
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* interrupts.
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*****************************************************************************/
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#define PLATFORM_G1S_PROPS(grp) \
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INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \
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grp, GIC_INTR_CFG_LEVEL)
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#define PLATFORM_G0_PROPS(grp)
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static const interrupt_prop_t stih410_interrupt_props[] = {
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PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0),
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PLATFORM_G0_PROPS(GICV2_INTR_GROUP0)
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};
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static unsigned int target_mask_array[PLATFORM_CORE_COUNT];
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static const struct gicv2_driver_data plat_gicv2_driver_data = {
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.gicd_base = GICD_BASE,
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.gicc_base = GICC_BASE,
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.interrupt_props = stih410_interrupt_props,
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.interrupt_props_num = ARRAY_SIZE(stih410_interrupt_props),
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.target_masks = target_mask_array,
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.target_masks_num = ARRAY_SIZE(target_mask_array),
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};
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/*******************************************************************************
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* Return a pointer to the 'entry_point_info' structure of the next image for
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* the security state specified. BL33 corresponds to the non-secure image type
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* while BL32 corresponds to the secure image type. A NULL pointer is returned
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* if the image does not exist.
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******************************************************************************/
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entry_point_info_t *sp_min_plat_get_bl33_ep_info(void)
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{
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entry_point_info_t *next_image_info = &bl33_image_ep_info;
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/*
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* None of the images on the ARM development platforms can have 0x0
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* as the entrypoint
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*/
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if (next_image_info->pc)
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return next_image_info;
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else
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return NULL;
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}
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void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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bl_params_t *params_from_bl2 = (bl_params_t *)arg0;
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/* Initialize the console to provide early debug support */
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console_init(PLAT_QEMU_BOOT_UART_BASE, PLAT_QEMU_BOOT_UART_CLK_IN_HZ,
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PLAT_QEMU_CONSOLE_BAUDRATE);
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ERROR("qemu sp_min, console init\n");
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/*
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* Check params passed from BL2
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*/
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assert(params_from_bl2);
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assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
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assert(params_from_bl2->h.version >= VERSION_2);
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bl_params_node_t *bl_params = params_from_bl2->head;
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/*
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* Copy BL33 entry point information from BL2's address space.
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*/
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while (bl_params) {
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if (bl_params->image_id == BL33_IMAGE_ID)
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bl33_image_ep_info = *bl_params->ep_info;
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bl_params = bl_params->next_params_info;
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}
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if (!bl33_image_ep_info.pc)
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panic();
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}
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void sp_min_plat_arch_setup(void)
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{
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qemu_configure_mmu_svc_mon(BL32_RO_BASE, BL32_END - BL32_RO_BASE,
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BL_CODE_BASE, BL_CODE_END,
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BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
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}
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void sp_min_platform_setup(void)
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{
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/* Initialize the gic cpu and distributor interfaces */
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gicv2_driver_init(&plat_gicv2_driver_data);
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gicv2_distif_init();
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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}
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unsigned int plat_get_syscnt_freq2(void)
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{
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return SYS_COUNTER_FREQ_IN_TICKS;
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}
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void sp_min_plat_fiq_handler(uint32_t id)
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{
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VERBOSE("[sp_min] interrupt #%d\n", id);
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}
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