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c703d752cc
SError and Abort are handled in Linux (EL1) instead of EL3. This patch adds some functionality that complements the use cases by Linux as follows: - Provide SMC for ECC DBE notification to EL3 - Determine type of reset needed and service the request in place of Linux Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com> Change-Id: I43d02c77f28004a31770be53599a5a42de412211
46 lines
966 B
C
46 lines
966 B
C
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved.
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*/
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#include <assert.h>
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#include <common/debug.h>
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#include <common/runtime_svc.h>
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#include <lib/mmio.h>
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#include <tools_share/uuid.h>
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#include "socfpga_fcs.h"
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#include "socfpga_mailbox.h"
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#include "socfpga_reset_manager.h"
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#include "socfpga_sip_svc.h"
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#include "socfpga_system_manager.h"
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uint32_t intel_ecc_dbe_notification(uint64_t dbe_value)
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{
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dbe_value &= WARM_RESET_WFI_FLAG;
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/* Trap CPUs in WFI if warm reset flag is set */
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if (dbe_value > 0) {
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while (1) {
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wfi();
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}
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}
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return INTEL_SIP_SMC_STATUS_OK;
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}
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bool cold_reset_for_ecc_dbe(void)
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{
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uint32_t dbe_int_status;
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dbe_int_status = mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8));
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/* Trigger cold reset only for error in critical memory (DDR/OCRAM) */
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dbe_int_status &= SYSMGR_ECC_DBE_COLD_RST_MASK;
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if (dbe_int_status > 0) {
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return true;
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}
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return false;
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}
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