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a29cb3c085
Change-Id: I6d26092525c2d5255a741515071ee7ed873aa52d Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
55 lines
2.6 KiB
C
55 lines
2.6 KiB
C
/*
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* Copyright (c) 2022-2023, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A510_H
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#define CORTEX_A510_H
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#define CORTEX_A510_MIDR U(0x410FD460)
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/*******************************************************************************
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* CPU Extended Control register specific definitions
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******************************************************************************/
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#define CORTEX_A510_CPUECTLR_EL1 S3_0_C15_C1_4
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#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT U(19)
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#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_WIDTH U(1)
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#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE U(1)
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#define CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT U(23)
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#define CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT U(46)
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#define CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR U(2)
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#define CORTEX_A510_CPUECTLR_EL1_ATOM_SHIFT U(38)
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#define CORTEX_A510_CPUECTLR_EL1_ATOM_WIDTH U(3)
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_A510_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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/*******************************************************************************
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* Complex auxiliary control register specific definitions
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******************************************************************************/
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#define CORTEX_A510_CMPXACTLR_EL1 S3_0_C15_C1_3
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#define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_DISABLE U(1)
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#define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_SHIFT U(25)
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#define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_WIDTH U(1)
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#define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_DISABLE U(3)
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#define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_SHIFT U(10)
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#define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_WIDTH U(2)
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/*******************************************************************************
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* Auxiliary control register specific definitions
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******************************************************************************/
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#define CORTEX_A510_CPUACTLR_EL1 S3_0_C15_C1_0
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#define CORTEX_A510_CPUACTLR_EL1_BIT_17 (ULL(1) << 17)
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#define CORTEX_A510_CPUACTLR_EL1_BIT_38 (ULL(1) << 38)
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#define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_DISABLE U(1)
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#define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_SHIFT U(18)
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#define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_WIDTH U(1)
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#define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_DISABLE U(1)
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#define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_SHIFT U(18)
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#define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_WIDTH U(1)
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#endif /* CORTEX_A510_H */
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