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https://github.com/ARM-software/arm-trusted-firmware.git
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a24b53e0e5
This patch mainly initializes the SPM and provides common APIs for SPM to enable the use of its various features. Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.com> Change-Id: I9facb6bf9962bb2d5fcacd945846bfaeb4c87a55
100 lines
2.6 KiB
C
100 lines
2.6 KiB
C
/*
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* Copyright (c) 2025, Mediatek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MT_SPM_SMC_H
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#define MT_SPM_SMC_H
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/*
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* SPM dispatcher's smc id definition
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* Please adding custom smc id here for spm dispatcher
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*/
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#define MT_SPM_STATUS_SUSPEND_SLEEP BIT(27)
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enum mt_spm_smc_uid {
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MT_SPM_SMC_UID_STATUS,
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MT_SPM_SMC_UID_PCM_WDT,
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MT_SPM_SMC_UID_PCM_TIMER,
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MT_SPM_SMC_UID_FW_TYPE,
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MT_SPM_SMC_UID_PHYPLL_MODE,
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MT_SPM_SMC_UID_SET_PENDING_IRQ_INIT,
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MT_SPM_SMC_UID_FW_INIT = 0x5731,
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};
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/*
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* SPM dbg dispatcher's smc id definition
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* Please adding custom smc id here for spm dbg dispatcher
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*/
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enum mt_spm_dbg_smc_uid {
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MT_SPM_DBG_SMC_UID_IDLE_PWR_CTRL,
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MT_SPM_DBG_SMC_UID_IDLE_CNT,
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MT_SPM_DBG_SMC_UID_SUSPEND_PWR_CTRL,
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MT_SPM_DBG_SMC_UID_SUSPEND_DBG_CTRL,
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MT_SPM_DBG_SMC_UID_FS,
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MT_SPM_DBG_SMC_UID_RC_SWITCH,
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MT_SPM_DBG_SMC_UID_RC_CNT,
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MT_SPM_DBG_SMC_UID_COND_CHECK,
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MT_SPM_DBG_SMC_UID_COND_BLOCK,
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MT_SPM_DBG_SMC_UID_BLOCK_LATCH,
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MT_SPM_DBG_SMC_UID_BLOCK_DETAIL,
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MT_SPM_DBG_SMC_UID_RES_NUM,
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MT_SPM_DBG_SMC_UID_RES_REQ,
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MT_SPM_DBG_SMC_UID_RES_USAGE,
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MT_SPM_DBG_SMC_UID_RES_USER_NUM,
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MT_SPM_DBG_SMC_UID_RES_USER_VALID,
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MT_SPM_DBG_SMC_UID_RES_USER_NAME,
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MT_SPM_DBG_SMC_UID_DOE_RESOURCE_CTRL,
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MT_SPM_DBG_SMC_UID_DOE_RC,
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MT_SPM_DBG_SMC_UID_RC_COND_CTRL,
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MT_SPM_DBG_SMC_UID_RC_RES_CTRL,
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MT_SPM_DBG_SMC_UID_RC_RES_INFO,
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MT_SPM_DBG_SMC_UID_RC_BBLPM,
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MT_SPM_DBG_SMC_UID_RC_TRACE,
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MT_SPM_DBG_SMC_UID_RC_TRACE_TIME,
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MT_SPM_DBG_SMC_UID_DUMP_PLL,
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MT_SPM_DBG_SMC_HWCG_NUM,
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MT_SPM_DBG_SMC_HWCG_STATUS,
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MT_SPM_DBG_SMC_HWCG_SETTING,
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MT_SPM_DBG_SMC_HWCG_DEF_SETTING,
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MT_SPM_DBG_SMC_HWCG_RES_NAME,
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MT_SPM_DBG_SMC_UID_RC_NOTIFY_CTRL,
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MT_SPM_DBG_SMC_VCORE_LP_ENABLE,
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MT_SPM_DBG_SMC_VCORE_LP_VOLT,
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MT_SPM_DBG_SMC_VSRAM_LP_ENABLE,
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MT_SPM_DBG_SMC_VSRAM_LP_VOLT,
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MT_SPM_DBG_SMC_PERI_REQ_NUM,
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MT_SPM_DBG_SMC_PERI_REQ_STATUS,
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MT_SPM_DBG_SMC_PERI_REQ_SETTING,
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MT_SPM_DBG_SMC_PERI_REQ_DEF_SETTING,
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MT_SPM_DBG_SMC_PERI_REQ_RES_NAME,
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MT_SPM_DBG_SMC_PERI_REQ_STATUS_RAW,
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MT_SPM_DBG_SMC_IDLE_PWR_STAT,
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MT_SPM_DBG_SMC_SUSPEND_PWR_STAT,
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MT_SPM_DBG_SMC_LP_REQ_STAT,
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MT_SPM_DBG_SMC_COMMON_SODI_CTRL,
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MT_SPM_DBG_SMC_SPM_TIMESTAMP,
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MT_SPM_DBG_SMC_SPM_TIMESTAMP_SIZE,
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MT_SPM_DBG_SMC_UID_COMMON_SODI_PWR_CTRL,
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};
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enum wake_status_enum {
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WAKE_STA_ASSERT_PC,
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WAKE_STA_R12,
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WAKE_STA_R12_EXT,
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WAKE_STA_RAW_STA,
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WAKE_STA_RAW_EXT_STA,
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WAKE_STA_WAKE_MISC,
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WAKE_STA_TIMER_OUT,
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WAKE_STA_R13,
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WAKE_STA_IDLE_STA,
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WAKE_STA_REQ_STA,
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WAKE_STA_DEBUG_FLAG,
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WAKE_STA_DEBUG_FLAG1,
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WAKE_STA_EVENT_REG,
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WAKE_STA_ISR,
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WAKE_STA_MAX_COUNT,
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};
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#endif /* MT_SPM_SMC_H */
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