Jayanth Dodderi Chidanand a0d9a973a4 chore(cm): reorganise sctlr_el1 and tcr_el1 ctx code ... SCTLR_EL1 and TCR_EL1 regs are included either as part of errata "ERRATA_SPECULATIVE_AT" or under el1_sysregs_t context structure. The code to write and read into these context entries, looks repetitive and is invoked at most places. This section is refactored to bring them under a static procedure, keeping the code neat and easier to maintain. Change-Id: Ib0d8c51bee09e1600c5baaa7f9745083dca9fee1 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>		2024-08-21 08:45:25 +01:00
..
aarch32	refactor(cpufeat): add macro to simplify is_feat_xx_present	2024-05-02 12:16:16 -05:00
aarch64	chore(cm): reorganise sctlr_el1 and tcr_el1 ctx code	2024-08-21 08:45:25 +01:00
cpu_data_array.c	chore: update to use Arm word across TF-A	2023-08-08 15:12:30 +01:00
simd_ctx.c	feat(simd): introduce simd context helper APIs	2024-08-19 11:10:10 -05:00