Jayanth Dodderi Chidanand a0d9a973a4 chore(cm): reorganise sctlr_el1 and tcr_el1 ctx code ... SCTLR_EL1 and TCR_EL1 regs are included either as part of errata "ERRATA_SPECULATIVE_AT" or under el1_sysregs_t context structure. The code to write and read into these context entries, looks repetitive and is invoked at most places. This section is refactored to bring them under a static procedure, keeping the code neat and easier to maintain. Change-Id: Ib0d8c51bee09e1600c5baaa7f9745083dca9fee1 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>		2024-08-21 08:45:25 +01:00
..
aarch32	chore: update to use Arm word across TF-A	2023-08-08 15:12:30 +01:00
aarch64	chore(cm): reorganise sctlr_el1 and tcr_el1 ctx code	2024-08-21 08:45:25 +01:00
context_debug.h	feat(context-mgmt): report context memory usage	2023-12-29 14:37:14 +00:00
context_el1.h	refactor(cm): convert el1-ctx assembly offset entries to c structure	2024-07-26 17:08:12 +01:00
context_el2.h	feat(fgt2): add support for FEAT_FGT2	2024-07-18 13:49:43 -05:00
context_mgmt.h	feat(cm): support for asymmetric feature among cores	2024-08-17 09:35:53 +01:00
cpu_data.h	feat(rme): add context management changes for FEAT_RME	2021-10-05 18:41:35 +02:00
pubsub.h	build: always prefix section names with .	2023-02-20 18:29:33 +00:00
pubsub_events.h	chore: update to use Arm word across TF-A	2023-08-08 15:12:30 +01:00
simd_ctx.h	feat(simd): add sve state to simd ctxt struct	2024-08-19 11:10:10 -05:00