mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-18 10:34:19 +00:00
a0cd989dd5
This patch factors out the ARM FVP specific code to create MMU translation tables so that it is possible for a boot loader stage to create a different set of tables instead of using the default ones. The default translation tables are created with the assumption that the calling boot loader stage executes out of secure SRAM. This might not be true for the BL3_2 stage in the future. A boot loader stage can define the `fill_xlation_tables()` function as per its requirements. It returns a reference to the level 1 translation table which is used by the common platform code to setup the TTBR_EL3. This patch is a temporary solution before a larger rework of translation table creation logic is introduced. Change-Id: I09a075d5da16822ee32a411a9dbe284718fb4ff6
326 lines
9.8 KiB
C
326 lines
9.8 KiB
C
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_H__
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#define __ARCH_H__
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#include <bl_common.h>
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/*******************************************************************************
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* MIDR bit definitions
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******************************************************************************/
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#define MIDR_PN_MASK 0xfff
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#define MIDR_PN_SHIFT 0x4
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#define MIDR_PN_AEM 0xd0f
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#define MIDR_PN_A57 0xd07
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#define MIDR_PN_A53 0xd03
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/*******************************************************************************
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* MPIDR macros
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******************************************************************************/
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#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
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#define MPIDR_CLUSTER_MASK MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS
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#define MPIDR_AFFINITY_BITS 8
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#define MPIDR_AFFLVL_MASK 0xff
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#define MPIDR_AFF0_SHIFT 0
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#define MPIDR_AFF1_SHIFT 8
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#define MPIDR_AFF2_SHIFT 16
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#define MPIDR_AFF3_SHIFT 32
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#define MPIDR_AFFINITY_MASK 0xff00ffffff
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#define MPIDR_AFFLVL_SHIFT 3
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#define MPIDR_AFFLVL0 0
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#define MPIDR_AFFLVL1 1
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#define MPIDR_AFFLVL2 2
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#define MPIDR_AFFLVL3 3
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/* TODO: Support only the first 3 affinity levels for now */
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#define MPIDR_MAX_AFFLVL 2
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/* Constant to highlight the assumption that MPIDR allocation starts from 0 */
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#define FIRST_MPIDR 0
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/*******************************************************************************
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* Implementation defined sysreg encodings
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******************************************************************************/
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#define CPUECTLR_EL1 S3_1_C15_C2_1
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/*******************************************************************************
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* Generic timer memory mapped registers & offsets
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******************************************************************************/
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#define CNTCR_OFF 0x000
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#define CNTFID_OFF 0x020
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#define CNTCR_EN (1 << 0)
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#define CNTCR_HDBG (1 << 1)
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#define CNTCR_FCREQ(x) (1 << (8 + (x)))
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/*******************************************************************************
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* System register bit definitions
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******************************************************************************/
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/* CLIDR definitions */
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#define LOUIS_SHIFT 21
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#define LOC_SHIFT 24
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#define CLIDR_FIELD_WIDTH 3
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/* CSSELR definitions */
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#define LEVEL_SHIFT 1
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/* D$ set/way op type defines */
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#define DCISW 0x0
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#define DCCISW 0x1
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#define DCCSW 0x2
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/* ID_AA64PFR0_EL1 definitions */
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#define ID_AA64PFR0_EL0_SHIFT 0
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#define ID_AA64PFR0_EL1_SHIFT 4
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#define ID_AA64PFR0_EL2_SHIFT 8
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#define ID_AA64PFR0_EL3_SHIFT 12
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#define ID_AA64PFR0_ELX_MASK 0xf
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/* ID_PFR1_EL1 definitions */
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#define ID_PFR1_VIRTEXT_SHIFT 12
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#define ID_PFR1_VIRTEXT_MASK 0xf
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#define GET_VIRT_EXT(id) ((id >> ID_PFR1_VIRTEXT_SHIFT) \
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& ID_PFR1_VIRTEXT_MASK)
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/* SCTLR definitions */
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#define SCTLR_EL2_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \
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(1 << 18) | (1 << 16) | (1 << 11) | (1 << 5) | \
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(1 << 4))
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#define SCTLR_EL1_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \
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(1 << 11))
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#define SCTLR_M_BIT (1 << 0)
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#define SCTLR_A_BIT (1 << 1)
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#define SCTLR_C_BIT (1 << 2)
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#define SCTLR_SA_BIT (1 << 3)
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#define SCTLR_B_BIT (1 << 7)
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#define SCTLR_Z_BIT (1 << 11)
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#define SCTLR_I_BIT (1 << 12)
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#define SCTLR_WXN_BIT (1 << 19)
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#define SCTLR_EXCEPTION_BITS (0x3 << 6)
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#define SCTLR_EE_BIT (1 << 25)
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/* CPUECTLR definitions */
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#define CPUECTLR_SMP_BIT (1 << 6)
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/* CPACR_El1 definitions */
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#define CPACR_EL1_FPEN(x) (x << 20)
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#define CPACR_EL1_FP_TRAP_EL0 0x1
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#define CPACR_EL1_FP_TRAP_ALL 0x2
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#define CPACR_EL1_FP_TRAP_NONE 0x3
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/* SCR definitions */
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#define SCR_RES1_BITS ((1 << 4) | (1 << 5))
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#define SCR_TWE_BIT (1 << 13)
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#define SCR_TWI_BIT (1 << 12)
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#define SCR_ST_BIT (1 << 11)
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#define SCR_RW_BIT (1 << 10)
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#define SCR_SIF_BIT (1 << 9)
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#define SCR_HCE_BIT (1 << 8)
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#define SCR_SMD_BIT (1 << 7)
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#define SCR_EA_BIT (1 << 3)
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#define SCR_FIQ_BIT (1 << 2)
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#define SCR_IRQ_BIT (1 << 1)
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#define SCR_NS_BIT (1 << 0)
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/* HCR definitions */
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#define HCR_RW_BIT (1ull << 31)
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#define HCR_AMO_BIT (1 << 5)
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#define HCR_IMO_BIT (1 << 4)
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#define HCR_FMO_BIT (1 << 3)
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/* CNTHCTL_EL2 definitions */
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#define EL1PCEN_BIT (1 << 1)
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#define EL1PCTEN_BIT (1 << 0)
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/* CNTKCTL_EL1 definitions */
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#define EL0PTEN_BIT (1 << 9)
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#define EL0VTEN_BIT (1 << 8)
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#define EL0PCTEN_BIT (1 << 0)
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#define EL0VCTEN_BIT (1 << 1)
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/* CPTR_EL3 definitions */
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#define TCPAC_BIT (1 << 31)
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#define TTA_BIT (1 << 20)
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#define TFP_BIT (1 << 10)
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/* CPSR/SPSR definitions */
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#define DAIF_FIQ_BIT (1 << 0)
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#define DAIF_IRQ_BIT (1 << 1)
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#define DAIF_ABT_BIT (1 << 2)
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#define DAIF_DBG_BIT (1 << 3)
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#define PSR_DAIF_SHIFT 0x6
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/*
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* TCR defintions
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*/
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#define TCR_EL3_RES1 ((1UL << 31) | (1UL << 23))
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#define TCR_T0SZ_4GB 32
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#define TCR_RGN_INNER_NC (0x0 << 8)
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#define TCR_RGN_INNER_WBA (0x1 << 8)
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#define TCR_RGN_INNER_WT (0x2 << 8)
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#define TCR_RGN_INNER_WBNA (0x3 << 8)
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#define TCR_RGN_OUTER_NC (0x0 << 10)
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#define TCR_RGN_OUTER_WBA (0x1 << 10)
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#define TCR_RGN_OUTER_WT (0x2 << 10)
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#define TCR_RGN_OUTER_WBNA (0x3 << 10)
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#define TCR_SH_NON_SHAREABLE (0x0 << 12)
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#define TCR_SH_OUTER_SHAREABLE (0x2 << 12)
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#define TCR_SH_INNER_SHAREABLE (0x3 << 12)
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#define MODE_RW_64 0x0
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#define MODE_RW_32 0x1
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#define MODE_SP_EL0 0x0
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#define MODE_SP_ELX 0x1
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#define MODE_EL3 0x3
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#define MODE_EL2 0x2
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#define MODE_EL1 0x1
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#define MODE_EL0 0x0
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#define MODE_RW_SHIFT 0x4
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#define MODE_EL_SHIFT 0x2
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#define MODE_SP_SHIFT 0x0
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#define GET_RW(mode) ((mode >> MODE_RW_SHIFT) & 0x1)
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#define GET_EL(mode) ((mode >> MODE_EL_SHIFT) & 0x3)
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#define PSR_MODE(rw, el, sp) (rw << MODE_RW_SHIFT | el << MODE_EL_SHIFT \
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| sp << MODE_SP_SHIFT)
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#define SPSR32_EE_BIT (1 << 9)
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#define SPSR32_T_BIT (1 << 5)
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#define AARCH32_MODE_SVC 0x13
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#define AARCH32_MODE_HYP 0x1a
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/* Miscellaneous MMU related constants */
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#define NUM_2MB_IN_GB (1 << 9)
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#define NUM_4K_IN_2MB (1 << 9)
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#define NUM_GB_IN_4GB (1 << 2)
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#define TWO_MB_SHIFT 21
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#define ONE_GB_SHIFT 30
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#define FOUR_KB_SHIFT 12
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#define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT)
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#define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT)
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#define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT)
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#define INVALID_DESC 0x0
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#define BLOCK_DESC 0x1
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#define TABLE_DESC 0x3
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#define FIRST_LEVEL_DESC_N ONE_GB_SHIFT
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#define SECOND_LEVEL_DESC_N TWO_MB_SHIFT
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#define THIRD_LEVEL_DESC_N FOUR_KB_SHIFT
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#define LEVEL1 1
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#define LEVEL2 2
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#define LEVEL3 3
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#define XN (1ull << 2)
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#define PXN (1ull << 1)
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#define CONT_HINT (1ull << 0)
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#define UPPER_ATTRS(x) (x & 0x7) << 52
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#define NON_GLOBAL (1 << 9)
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#define ACCESS_FLAG (1 << 8)
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#define NSH (0x0 << 6)
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#define OSH (0x2 << 6)
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#define ISH (0x3 << 6)
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#define IS_PAGE_ALIGNED(addr) (((addr) & 0xFFF) == 0)
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/*
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* AP[1] bit is ignored by hardware and is
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* treated as if it is One in EL2/EL3
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*/
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#define AP_RO (0x1 << 5)
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#define AP_RW (0x0 << 5)
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#define NS (0x1 << 3)
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#define ATTR_SO_INDEX 0x2
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#define ATTR_DEVICE_INDEX 0x1
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#define ATTR_IWBWA_OWBWA_NTR_INDEX 0x0
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#define LOWER_ATTRS(x) (((x) & 0xfff) << 2)
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#define ATTR_SO (0x0)
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#define ATTR_DEVICE (0x4)
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#define ATTR_IWBWA_OWBWA_NTR (0xff)
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#define MAIR_ATTR_SET(attr, index) (attr << (index << 3))
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/* Exception Syndrome register bits and bobs */
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#define ESR_EC_SHIFT 26
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#define ESR_EC_MASK 0x3f
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#define ESR_EC_LENGTH 6
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#define EC_UNKNOWN 0x0
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#define EC_WFE_WFI 0x1
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#define EC_AARCH32_CP15_MRC_MCR 0x3
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#define EC_AARCH32_CP15_MRRC_MCRR 0x4
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#define EC_AARCH32_CP14_MRC_MCR 0x5
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#define EC_AARCH32_CP14_LDC_STC 0x6
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#define EC_FP_SIMD 0x7
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#define EC_AARCH32_CP10_MRC 0x8
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#define EC_AARCH32_CP14_MRRC_MCRR 0xc
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#define EC_ILLEGAL 0xe
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#define EC_AARCH32_SVC 0x11
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#define EC_AARCH32_HVC 0x12
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#define EC_AARCH32_SMC 0x13
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#define EC_AARCH64_SVC 0x15
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#define EC_AARCH64_HVC 0x16
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#define EC_AARCH64_SMC 0x17
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#define EC_AARCH64_SYS 0x18
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#define EC_IABORT_LOWER_EL 0x20
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#define EC_IABORT_CUR_EL 0x21
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#define EC_PC_ALIGN 0x22
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#define EC_DABORT_LOWER_EL 0x24
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#define EC_DABORT_CUR_EL 0x25
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#define EC_SP_ALIGN 0x26
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#define EC_AARCH32_FP 0x28
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#define EC_AARCH64_FP 0x2c
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#define EC_SERROR 0x2f
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#define EC_BITS(x) (x >> ESR_EC_SHIFT) & ESR_EC_MASK
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#ifndef __ASSEMBLY__
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/*******************************************************************************
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* Function prototypes
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******************************************************************************/
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extern void early_exceptions(void);
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extern void runtime_exceptions(void);
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extern void bl1_arch_setup(void);
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extern void bl2_arch_setup(void);
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extern void bl31_arch_setup(void);
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#endif /*__ASSEMBLY__*/
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#endif /* __ARCH_H__ */
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