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a02bb36caa
TC is getting an FPGA port alongside the FVP. It is meant to be identical, but the core configurations on TC2 differ (there are 14 in an odd arrangement). Introduce these differences and gate them behind a new TARGET_FLAVOUR flag which defaults to FVP for compatibility. While updating CPUs, it's a good time to do TC3 too. It has different cores in a different configuration again, so it needs different capacity values. Those have been derived using GeekBench 6.0 ST on the FPGA. Finally GPU and DPU power domains are 1 above the CPUs so make that relative. In the end, the big/mid/little configurations are: * TC2 FVP: 1/3/4 * TC2 FPGA: 2/3/5/4 (the 3 is a big "min" core) * TC3 both: 2/4/2 (with new capacities) Co-developed-by: Tintu Thomas <tintu.thomas@arm.com> Co-developed-by: Kshitij Sisodia <kshitij.sisodia@arm.com> Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I3c3a10d6727f5010fd9026a404df27e9262dff6b
52 lines
1.4 KiB
Text
52 lines
1.4 KiB
Text
/*
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* Copyright (c) 2023-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#define GPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 1)
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#define DPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 2)
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/* All perf is normalized against the big core */
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#define BIG_CAPACITY 1024
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#if TARGET_PLATFORM <= 2
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#if TARGET_FLAVOUR_FVP
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#define LIT_CAPACITY 406
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#define MID_CAPACITY 912
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#else /* TARGET_FLAVOUR_FPGA */
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#define LIT_CAPACITY 280
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#define MID_CAPACITY 775
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/* this is an area optimized configuration of the big core */
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#define BIG2_CAPACITY 930
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#endif /* TARGET_FLAVOUR_FPGA */
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#define INT_MBOX_RX 317
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#define MHU_TX_ADDR(pref) pref##45000000 /* hex */
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#define MHU_RX_ADDR(pref) pref##45010000 /* hex */
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#define MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */
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#define UARTCLK_FREQ 5000000
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#elif TARGET_PLATFORM == 3
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#define LIT_CAPACITY 239
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#define MID_CAPACITY 686
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#define INT_MBOX_RX 300
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#define MHU_TX_ADDR(pref) pref##46040000 /* hex */
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#define MHU_RX_ADDR(pref) pref##46140000 /* hex */
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#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
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#define UARTCLK_FREQ 3750000
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#endif /* TARGET_PLATFORM == 3 */
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/ {
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#if TARGET_PLATFORM <= 2
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cmn-pmu {
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compatible = "arm,ci-700";
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reg = <0x0 0x50000000 0x0 0x10000000>;
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interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
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};
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#endif /* TARGET_PLATFORM <= 2 */
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};
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