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https://github.com/ARM-software/arm-trusted-firmware.git
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9fd9f1d024
RK3566/RK3568 is a Quad-core soc and Cortex-a55 inside. This patch supports the following functions: 1. basic platform setup 2. power up/off cpus 3. suspend/resume cpus 4. suspend/resume system 5. reset system Signed-off-by: shengfei Xu <xsf@rock-chips.com> Change-Id: I8b98a4d07664de26bd6078f63664cbc3d9c1c68c
104 lines
3.2 KiB
C
104 lines
3.2 KiB
C
/*
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* Copyright (c) 2023, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __PLAT_DEF_H__
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#define __PLAT_DEF_H__
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#define MAJOR_VERSION (1)
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#define MINOR_VERSION (0)
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#define SIZE_K(n) ((n) * 1024)
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/* Special value used to verify platform parameters from BL2 to BL3-1 */
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#define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
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#define GIC600_BASE 0xfd400000
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#define GIC600_SIZE SIZE_K(64)
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#define PMUSGRF_BASE 0xfdc00000
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#define SYSSGRF_BASE 0xfdc10000
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#define PMUGRF_BASE 0xfdc20000
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#define CPUGRF_BASE 0xfdc30000
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#define DDRGRF_BASE 0xfdc40000
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#define PIPEGRF_BASE 0xfdc50000
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#define GRF_BASE 0xfdc60000
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#define PIPEPHY_GRF0 0xfdc70000
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#define PIPEPHY_GRF1 0xfdc80000
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#define PIPEPHY_GRF2 0xfdc90000
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#define USBPHY_U3_GRF 0xfdca0000
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#define USB2PHY_U2_GRF 0xfdca8000
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#define EDPPHY_GRF 0xfdcb0000
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#define SYSSRAM_BASE 0xfdcc0000
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#define PCIE30PHY_GRF 0xfdcb8000
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#define USBGRF_BASE 0xfdcf0000
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#define PMUCRU_BASE 0xfdd00000
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#define SCRU_BASE 0xfdd10000
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#define SGRF_BASE 0xfdd18000
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#define STIME_BASE 0xfdd1c000
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#define CRU_BASE 0xfdd20000
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#define PMUSCRU_BASE 0xfdd30000
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#define I2C0_BASE 0xfdd40000
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#define UART0_BASE 0xfdd50000
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#define GPIO0_BASE 0xfdd60000
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#define PMUPVTM_BASE 0xfdd80000
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#define PMU_BASE 0xfdd90000
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#define PMUSRAM_BASE 0xfdcd0000
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#define PMUSRAM_SIZE SIZE_K(128)
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#define PMUSRAM_RSIZE SIZE_K(8)
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#define DDRSGRF_BASE 0xfe200000
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#define UART1_BASE 0xfe650000
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#define UART2_BASE 0xfe660000
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#define GPIO1_BASE 0xfe740000
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#define GPIO2_BASE 0xfe750000
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#define GPIO3_BASE 0xfe760000
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#define GPIO4_BASE 0xfe770000
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#define REMAP_BASE 0xffff0000
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#define REMAP_SIZE SIZE_K(64)
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/**************************************************************************
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* UART related constants
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**************************************************************************/
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#define FPGA_UART_BASE UART2_BASE
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#define FPGA_BAUDRATE 1500000
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#define FPGA_UART_CLOCK 24000000
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/******************************************************************************
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* System counter frequency related constants
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******************************************************************************/
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#define SYS_COUNTER_FREQ_IN_TICKS 24000000
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#define SYS_COUNTER_FREQ_IN_MHZ 24
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/******************************************************************************
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* GIC-600 & interrupt handling related constants
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******************************************************************************/
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/* Base rk_platform compatible GIC memory map */
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#define PLAT_GICD_BASE GIC600_BASE
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#define PLAT_GICC_BASE 0
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#define PLAT_GICR_BASE (GIC600_BASE + 0x60000)
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/******************************************************************************
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* sgi, ppi
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******************************************************************************/
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#define RK_IRQ_SEC_PHY_TIMER 29
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#define RK_IRQ_SEC_SGI_0 8
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#define RK_IRQ_SEC_SGI_1 9
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#define RK_IRQ_SEC_SGI_2 10
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#define RK_IRQ_SEC_SGI_3 11
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#define RK_IRQ_SEC_SGI_4 12
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#define RK_IRQ_SEC_SGI_5 13
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#define RK_IRQ_SEC_SGI_6 14
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#define RK_IRQ_SEC_SGI_7 15
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#define SHARE_MEM_BASE 0x100000/* [1MB, 1MB+60K]*/
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#define SHARE_MEM_PAGE_NUM 15
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#define SHARE_MEM_SIZE SIZE_K(SHARE_MEM_PAGE_NUM * 4)
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#endif /* __PLAT_DEF_H__ */
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