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RK3566/RK3568 is a Quad-core soc and Cortex-a55 inside. This patch supports the following functions: 1. basic platform setup 2. power up/off cpus 3. suspend/resume cpus 4. suspend/resume system 5. reset system Signed-off-by: shengfei Xu <xsf@rock-chips.com> Change-Id: I8b98a4d07664de26bd6078f63664cbc3d9c1c68c
96 lines
3 KiB
Makefile
96 lines
3 KiB
Makefile
#
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# Copyright (c) 2023, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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RK_PLAT := plat/rockchip
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RK_PLAT_SOC := ${RK_PLAT}/${PLAT}
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RK_PLAT_COMMON := ${RK_PLAT}/common
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DISABLE_BIN_GENERATION := 1
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GICV3_SUPPORT_GIC600 := 1
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include lib/coreboot/coreboot.mk
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include lib/libfdt/libfdt.mk
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include lib/xlat_tables_v2/xlat_tables.mk
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# GIC-600 configuration
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GICV3_IMPL := GIC600
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# Include GICv3 driver files
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include drivers/arm/gic/v3/gicv3.mk
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PLAT_INCLUDES := -Iinclude/bl31 \
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-Iinclude/common \
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-Iinclude/drivers \
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-Iinclude/drivers/arm \
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-Iinclude/drivers/auth \
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-Iinclude/drivers/io \
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-Iinclude/drivers/ti/uart \
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-Iinclude/lib \
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-Iinclude/lib/cpus/${ARCH} \
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-Iinclude/lib/el3_runtime \
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-Iinclude/lib/pmf \
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-Iinclude/lib/psci \
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-Iinclude/plat/common \
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-Iinclude/services \
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-Iinclude/plat/common/ \
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-Idrivers/arm/gic/v3/ \
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-I${RK_PLAT_COMMON}/ \
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-I${RK_PLAT_COMMON}/pmusram/ \
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-I${RK_PLAT_COMMON}/include/ \
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-I${RK_PLAT_COMMON}/drivers/pmu/ \
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-I${RK_PLAT_COMMON}/drivers/parameter/ \
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-I${RK_PLAT_SOC}/ \
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-I${RK_PLAT_SOC}/drivers/pmu/ \
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-I${RK_PLAT_SOC}/drivers/soc/ \
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-I${RK_PLAT_SOC}/include/
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RK_GIC_SOURCES := ${GICV3_SOURCES} \
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plat/common/plat_gicv3.c \
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${RK_PLAT}/common/rockchip_gicv3.c
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PLAT_BL_COMMON_SOURCES := ${XLAT_TABLES_LIB_SRCS} \
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common/desc_image_load.c \
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plat/common/aarch64/crash_console_helpers.S \
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lib/bl_aux_params/bl_aux_params.c \
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plat/common/plat_psci_common.c
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ifneq (${ENABLE_STACK_PROTECTOR},0)
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PLAT_BL_COMMON_SOURCES += ${RK_PLAT_COMMON}/rockchip_stack_protector.c
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endif
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BL31_SOURCES += ${RK_GIC_SOURCES} \
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drivers/arm/cci/cci.c \
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lib/cpus/aarch64/cortex_a55.S \
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drivers/ti/uart/aarch64/16550_console.S \
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drivers/delay_timer/delay_timer.c \
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drivers/delay_timer/generic_delay_timer.c \
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$(LIBFDT_SRCS) \
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${RK_PLAT_COMMON}/aarch64/plat_helpers.S \
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${RK_PLAT_COMMON}/bl31_plat_setup.c \
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${RK_PLAT_COMMON}/params_setup.c \
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${RK_PLAT_COMMON}/plat_pm.c \
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${RK_PLAT_COMMON}/plat_topology.c \
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${RK_PLAT_COMMON}/rockchip_sip_svc.c \
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${RK_PLAT_COMMON}/pmusram/cpus_on_fixed_addr.S \
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${RK_PLAT_COMMON}/drivers/parameter/ddr_parameter.c \
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${RK_PLAT_COMMON}/aarch64/platform_common.c \
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${RK_PLAT_SOC}/drivers/soc/soc.c \
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${RK_PLAT_SOC}/drivers/pmu/pmu.c \
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${RK_PLAT_SOC}/plat_sip_calls.c
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ENABLE_PLAT_COMPAT := 0
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MULTI_CONSOLE_API := 1
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# System coherency is managed in hardware
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HW_ASSISTED_COHERENCY := 1
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#Enable errata for cortex_a55
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ERRATA_A55_1530923 := 1
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# When building for systems with hardware-assisted coherency, there's no need to
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# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too.
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USE_COHERENT_MEM := 0
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$(eval $(call add_define,PLAT_SKIP_OPTEE_S_EL1_INT_REGISTER))
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$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
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# Do not enable SVE
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ENABLE_SVE_FOR_NS := 0
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