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9fd9f1d024
RK3566/RK3568 is a Quad-core soc and Cortex-a55 inside. This patch supports the following functions: 1. basic platform setup 2. power up/off cpus 3. suspend/resume cpus 4. suspend/resume system 5. reset system Signed-off-by: shengfei Xu <xsf@rock-chips.com> Change-Id: I8b98a4d07664de26bd6078f63664cbc3d9c1c68c
103 lines
2.8 KiB
C
103 lines
2.8 KiB
C
/*
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* Copyright (c) 2023, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <mmio.h>
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#include <platform_def.h>
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#include <soc.h>
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const mmap_region_t plat_rk_mmap[] = {
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MAP_REGION_FLAT(RKFPGA_DEV_RNG0_BASE, RKFPGA_DEV_RNG0_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE,
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MT_MEMORY | MT_RW | MT_SECURE),
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{ 0 }
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};
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/* The RockChip power domain tree descriptor */
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const unsigned char rockchip_power_domain_tree_desc[] = {
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/* No of root nodes */
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PLATFORM_SYSTEM_COUNT,
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/* No of children for the root node */
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PLATFORM_CLUSTER_COUNT,
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/* No of children for the first cluster node */
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PLATFORM_CLUSTER0_CORE_COUNT,
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};
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static void secure_timer_init(void)
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{
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mmio_write_32(STIMER0_CHN_BASE(1) + TIMER_CONTROL_REG, TIMER_DIS);
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mmio_write_32(STIMER0_CHN_BASE(1) + TIMER_LOAD_COUNT0, 0xffffffff);
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mmio_write_32(STIMER0_CHN_BASE(1) + TIMER_LOAD_COUNT1, 0xffffffff);
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/* auto reload & enable the timer */
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mmio_write_32(STIMER0_CHN_BASE(1) + TIMER_CONTROL_REG, TIMER_EN);
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}
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static void sgrf_init(void)
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{
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mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(0), 0xffff0000);
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mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(1), 0xffff0000);
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mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(2), 0xffff0000);
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mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(3), 0xffff0000);
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mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(4), 0xffff0000);
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mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(5), 0xffff0000);
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mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(6), 0xffff0000);
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mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(7), 0xffff0000);
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mmio_write_32(SGRF_BASE + SGRF_FIREWALL_SLV_CON(8), 0xffff0000);
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mmio_write_32(DDRSGRF_BASE + FIREWALL_DDR_FW_DDR_CON_REG, 0xffff0000);
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}
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static void set_pll_slow_mode(uint32_t clk_pll)
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{
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mmio_write_32(CRU_BASE + CRU_MODE_CON00, 0x03 << (16 + clk_pll * 2));
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}
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static void __dead2 soc_global_soft_reset(void)
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{
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set_pll_slow_mode(CLK_CPLL);
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set_pll_slow_mode(CLK_GPLL);
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set_pll_slow_mode(CLK_NPLL);
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set_pll_slow_mode(CLK_VPLL);
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set_pll_slow_mode(CLK_USBPLL);
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set_pll_slow_mode(CLK_APLL);
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mmio_write_32(PMUCRU_BASE + PMUCRU_MODE_CON00, 0x000f0000);
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dsb();
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mmio_write_32(CRU_BASE + CRU_GLB_SRST_FST, GLB_SRST_FST_CFG_VAL);
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/*
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* Maybe the HW needs some times to reset the system,
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* so we do not hope the core to excute valid codes.
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*/
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while (1) {
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;
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}
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}
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static void rockchip_system_reset_init(void)
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{
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mmio_write_32(GRF_BASE + 0x0508, 0x00100010);
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mmio_write_32(CRU_BASE + 0x00dc, 0x01030103);
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}
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void __dead2 rockchip_soc_soft_reset(void)
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{
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soc_global_soft_reset();
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}
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void plat_rockchip_soc_init(void)
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{
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secure_timer_init();
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sgrf_init();
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rockchip_system_reset_init();
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NOTICE("BL31: Rockchip release version: v%d.%d\n",
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MAJOR_VERSION, MINOR_VERSION);
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}
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