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https://github.com/ARM-software/arm-trusted-firmware.git
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9fd9f1d024
RK3566/RK3568 is a Quad-core soc and Cortex-a55 inside. This patch supports the following functions: 1. basic platform setup 2. power up/off cpus 3. suspend/resume cpus 4. suspend/resume system 5. reset system Signed-off-by: shengfei Xu <xsf@rock-chips.com> Change-Id: I8b98a4d07664de26bd6078f63664cbc3d9c1c68c
304 lines
6.1 KiB
C
304 lines
6.1 KiB
C
/*
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* Copyright (c) 2023, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __PMU_H__
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#define __PMU_H__
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#define PMU_VERSION 0x0000
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#define PMU_PWR_CON 0x0004
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#define PMU_MAIN_PWR_STATE 0x0008
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#define PMU_INT_MASK_CON 0x000C
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#define PMU_WAKEUP_INT_CON 0x0010
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#define PMU_WAKEUP_INT_ST 0x0014
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#define PMU_WAKEUP_EDGE_CON 0x0018
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#define PMU_WAKEUP_EDGE_ST 0x001C
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#define PMU_BUS_IDLE_CON0 0x0040
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#define PMU_BUS_IDLE_CON1 0x0044
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#define PMU_BUS_IDLE_SFTCON0 0x0050
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#define PMU_BUS_IDLE_SFTCON1 0x0054
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#define PMU_BUS_IDLE_ACK 0x0060
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#define PMU_BUS_IDLE_ST 0x0068
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#define PMU_NOC_AUTO_CON0 0x0070
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#define PMU_NOC_AUTO_CON1 0x0074
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#define PMU_DDR_PWR_CON 0x0080
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#define PMU_DDR_PWR_SFTCON 0x0084
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#define PMU_DDR_PWR_STATE 0x0088
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#define PMU_DDR_PWR_ST 0x008C
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#define PMU_PWR_GATE_CON 0x0090
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#define PMU_PWR_GATE_STATE 0x0094
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#define PMU_PWR_DWN_ST 0x0098
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#define PMU_PWR_GATE_SFTCON 0x00A0
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#define PMU_VOL_GATE_SFTCON 0x00A8
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#define PMU_CRU_PWR_CON 0x00B0
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#define PMU_CRU_PWR_SFTCON 0x00B4
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#define PMU_CRU_PWR_STATE 0x00B8
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#define PMU_PLLPD_CON 0x00C0
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#define PMU_PLLPD_SFTCON 0x00C4
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#define PMU_INFO_TX_CON 0x00D0
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#define PMU_DSU_STABLE_CNT 0x0100
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#define PMU_PMIC_STABLE_CNT 0x0104
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#define PMU_OSC_STABLE_CNT 0x0108
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#define PMU_WAKEUP_RSTCLR_CNT 0x010C
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#define PMU_PLL_LOCK_CNT 0x0110
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#define PMU_DSU_PWRUP_CNT 0x0118
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#define PMU_DSU_PWRDN_CNT 0x011C
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#define PMU_GPU_VOLUP_CNT 0x0120
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#define PMU_GPU_VOLDN_CNT 0x0124
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#define PMU_WAKEUP_TIMEOUT_CNT 0x0128
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#define PMU_PWM_SWITCH_CNT 0x012C
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#define PMU_DBG_RST_CNT 0x0130
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#define PMU_SYS_REG0 0x0180
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#define PMU_SYS_REG1 0x0184
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#define PMU_SYS_REG2 0x0188
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#define PMU_SYS_REG3 0x018C
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#define PMU_SYS_REG4 0x0190
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#define PMU_SYS_REG5 0x0194
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#define PMU_SYS_REG6 0x0198
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#define PMU_SYS_REG7 0x019C
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#define PMU_DSU_PWR_CON 0x0300
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#define PMU_DSU_PWR_SFTCON 0x0304
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#define PMU_DSU_AUTO_CON 0x0308
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#define PMU_DSU_PWR_STATE 0x030C
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#define PMU_CPU_AUTO_PWR_CON0 0x0310
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#define PMU_CPU_AUTO_PWR_CON1 0x0314
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#define PMU_CPU_PWR_SFTCON 0x0318
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#define PMU_CLUSTER_PWR_ST 0x031C
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#define PMU_CLUSTER_IDLE_CON 0x0320
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#define PMU_CLUSTER_IDLE_SFTCON 0x0324
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#define PMU_CLUSTER_IDLE_ACK 0x0328
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#define PMU_CLUSTER_IDLE_ST 0x032C
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#define PMU_DBG_PWR_CON 0x0330
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/* PMU_SGRF */
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#define PMU_SGRF_SOC_CON1 0x0004
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#define PMU_SGRF_FAST_BOOT_ADDR 0x0180
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/* sys grf */
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#define GRF_CPU_STATUS0 0x0420
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#define CRU_SOFTRST_CON00 0x0400
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#define CORES_PM_DISABLE 0x0
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#define PD_CHECK_LOOP 500
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#define WFEI_CHECK_LOOP 500
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#define PMUSGRF_SOC_CON(i) ((i) * 0x4)
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/* Needed aligned 16 bytes for sp stack top */
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#define PSRAM_SP_TOP ((PMUSRAM_BASE + PMUSRAM_RSIZE) & ~0xf)
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#define PMU_CPUAPM_CON(cpu) (0x0310 + (cpu) * 0x4)
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#define PMIC_SLEEP_FUN 0x07000100
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#define PMIC_SLEEP_GPIO 0x07000000
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#define GPIO_SWPORT_DR_L 0x0000
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#define GPIO_SWPORT_DR_H 0x0004
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#define GPIO_SWPORT_DDR_L 0x0008
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#define GPIO_SWPORT_DDR_H 0x000C
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#define PMIC_SLEEP_HIGH_LEVEL 0x00040004
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#define PMIC_SLEEP_LOW_LEVEL 0x00040000
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#define PMIC_SLEEP_OUT 0x00040004
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#define CPUS_BYPASS 0x007e4f7e
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#define CLB_INT_DISABLE 0x00010001
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#define WRITE_MASK_SET(value) ((value << 16) | value)
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#define WRITE_MASK_CLR(value) ((value << 16))
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enum pmu_cores_pm_by_wfi {
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core_pm_en = 0,
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core_pm_int_wakeup_en,
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core_pm_int_wakeup_glb_msk,
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core_pm_sft_wakeup_en,
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};
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/* The ways of cores power domain contorlling */
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enum cores_pm_ctr_mode {
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core_pwr_pd = 0,
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core_pwr_wfi = 1,
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core_pwr_wfi_int = 2
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};
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/* PMU_PWR_DWN_ST */
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enum pmu_pdid {
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PD_GPU,
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PD_NPU,
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PD_VPU,
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PD_RKVENC,
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PD_RKVDEC,
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PD_RGA,
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PD_VI,
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PD_VO,
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PD_PIPE,
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PD_CENTER,
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PD_END
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};
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/* PMU_PWR_CON */
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enum pmu_pwr_con {
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POWRMODE_EN,
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DSU_BYPASS,
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BUS_BYPASS = 4,
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DDR_BYPASS,
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PWRDN_BYPASS,
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CRU_BYPASS,
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CPU0_BYPASS,
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CPU1_BYPASS,
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CPU2_BYPASS,
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CPU3_BYPASS,
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PMU_SLEEP_LOW = 15,
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};
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/* PMU_CRU_PWR_CON */
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enum pmu_cru_pwr_con {
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ALIVE_32K_ENA,
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OSC_DIS_ENA,
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WAKEUP_RST_ENA,
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INPUT_CLAMP_ENA,
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ALIVE_OSC_ENA,
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POWER_OFF_ENA,
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PWM_SWITCH_ENA,
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PWM_GPIO_IOE_ENA,
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PWM_SWITCH_IOUT,
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PD_BUS_CLK_SRC_GATE_ENA,
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PD_PERI_CLK_SRC_GATE_ENA,
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PD_PMU_CLK_SRC_GATE_ENA,
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PMUMEM_CLK_SRC_GATE_ENA,
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PWR_CON_END
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};
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/* PMU_PLLPD_CON */
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enum pmu_pllpd_con {
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APLL_PD_ENA,
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DPLL_PD_ENA,
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CPLL_PD_ENA,
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GPLL_PD_ENA,
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MPLL_PD_ENA,
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NPLL_PD_ENA,
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HPLL_PD_ENA,
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PPLL_PD_ENA,
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VPLL_PD_ENA,
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PLL_PD_END
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};
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/* PMU_DSU_PWR_CON */
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enum pmu_dsu_pwr_con {
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DSU_PWRDN_ENA = 2,
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DSU_PWROFF_ENA,
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DSU_RET_ENA = 6,
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CLUSTER_CLK_SRC_GATE_ENA,
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DSU_PWR_CON_END
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};
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enum cpu_power_state {
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CPU_POWER_ON,
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CPU_POWER_OFF,
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CPU_EMULATION_OFF,
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CPU_RETENTION,
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CPU_DEBUG
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};
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enum dsu_power_state {
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DSU_POWER_ON,
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CLUSTER_TRANSFER_IDLE,
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DSU_POWER_DOWN,
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DSU_OFF,
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DSU_WAKEUP,
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DSU_POWER_UP,
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CLUSTER_TRANSFER_RESUME,
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DSU_FUNCTION_RETENTION
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};
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enum pmu_wakeup_int_con {
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WAKEUP_CPU0_INT_EN,
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WAKEUP_CPU1_INT_EN,
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WAKEUP_CPU2_INT_EN,
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WAKEUP_CPU3_INT_EN,
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WAKEUP_GPIO0_INT_EN,
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WAKEUP_UART0_EN,
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WAKEUP_SDMMC0_EN,
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WAKEUP_SDMMC1_EN,
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WAKEUP_SDMMC2_EN,
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WAKEUP_USB_EN,
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WAKEUP_PCIE_EN,
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WAKEUP_VAD_EN,
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WAKEUP_TIMER_EN,
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WAKEUP_PWM0_EN,
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WAKEUP_TIMEROUT_EN,
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WAKEUP_MCU_SFT_EN,
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};
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enum pmu_wakeup_int_st {
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WAKEUP_CPU0_INT_ST,
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WAKEUP_CPU1_INT_ST,
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WAKEUP_CPU2_INT_ST,
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WAKEUP_CPU3_INT_ST,
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WAKEUP_GPIO0_INT_ST,
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WAKEUP_UART0_ST,
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WAKEUP_SDMMC0_ST,
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WAKEUP_SDMMC1_ST,
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WAKEUP_SDMMC2_ST,
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WAKEUP_USB_ST,
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WAKEUP_PCIE_ST,
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WAKEUP_VAD_ST,
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WAKEUP_TIMER_ST,
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WAKEUP_PWM0_ST,
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WAKEUP_TIMEOUT_ST,
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WAKEUP_SYS_INT_ST,
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};
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enum pmu_bus_idle_con0 {
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IDLE_REQ_MSCH,
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IDLE_REQ_GPU,
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IDLE_REQ_NPU,
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IDLE_REQ_VI,
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IDLE_REQ_VO,
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IDLE_REQ_RGA,
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IDLE_REQ_VPU,
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IDLE_REQ_RKVENC,
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IDLE_REQ_RKVDEC,
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IDLE_REQ_GIC_AUDIO,
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IDLE_REQ_PHP,
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IDLE_REQ_PIPE,
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IDLE_REQ_SECURE_FLASH,
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IDLE_REQ_PERIMID,
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IDLE_REQ_USB,
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IDLE_REQ_BUS,
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};
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enum pmu_bus_idle_con1 {
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IDLE_REQ_TOP1,
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IDLE_REQ_TOP2,
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IDLE_REQ_PMU,
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};
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enum pmu_pwr_gate_con {
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PD_GPU_DWN_ENA,
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PD_NPU_DWN_ENA,
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PD_VPU_DWN_ENA,
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PD_RKVENC_DWN_ENA,
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PD_RKVDEC_DWN_ENA,
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PD_RGA_DWN_ENA,
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PD_VI_DWN_ENA,
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PD_VO_DWN_ENA,
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PD_PIPE_DWN_ENA,
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PD_CENTER_DWN_ENA,
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};
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enum pmu_ddr_pwr_con {
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DDR_SREF_ENA,
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DDRIO_RET_ENTER_ENA,
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DDRIO_RET_EXIT_ENA = 2,
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DDRPHY_AUTO_GATING_ENA = 4,
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};
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enum pmu_vol_gate_soft_con {
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VD_GPU_ENA,
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VD_NPU_ENA,
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};
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#endif /* __PMU_H__ */
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