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9fd9f1d024
RK3566/RK3568 is a Quad-core soc and Cortex-a55 inside. This patch supports the following functions: 1. basic platform setup 2. power up/off cpus 3. suspend/resume cpus 4. suspend/resume system 5. reset system Signed-off-by: shengfei Xu <xsf@rock-chips.com> Change-Id: I8b98a4d07664de26bd6078f63664cbc3d9c1c68c
86 lines
2.2 KiB
C
86 lines
2.2 KiB
C
/*
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* Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <string.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <drivers/arm/cci.h>
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#include <lib/utils.h>
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#include <plat_private.h>
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#ifdef PLAT_RK_CCI_BASE
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static const int cci_map[] = {
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PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX,
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PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX
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};
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#endif
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/******************************************************************************
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* Macro generating the code for the function setting up the pagetables as per
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* the platform memory map & initialize the mmu, for the given exception level
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******************************************************************************/
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#define DEFINE_CONFIGURE_MMU_EL(_el) \
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void plat_configure_mmu_el ## _el(unsigned long total_base, \
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unsigned long total_size, \
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unsigned long ro_start, \
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unsigned long ro_limit, \
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unsigned long coh_start, \
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unsigned long coh_limit) \
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{ \
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mmap_add_region(total_base, total_base, \
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total_size, \
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MT_MEMORY | MT_RW | MT_SECURE); \
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mmap_add_region(ro_start, ro_start, \
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ro_limit - ro_start, \
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MT_MEMORY | MT_RO | MT_SECURE); \
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if ((coh_limit - coh_start) != 0) \
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mmap_add_region(coh_start, coh_start, \
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coh_limit - coh_start, \
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MT_DEVICE | MT_RW | MT_SECURE); \
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mmap_add(plat_rk_mmap); \
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rockchip_plat_mmu_el##_el(); \
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init_xlat_tables(); \
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\
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enable_mmu_el ## _el(0); \
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}
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/* Define EL3 variants of the function initialising the MMU */
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DEFINE_CONFIGURE_MMU_EL(3)
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unsigned int plat_get_syscnt_freq2(void)
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{
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return SYS_COUNTER_FREQ_IN_TICKS;
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}
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void plat_cci_init(void)
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{
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#ifdef PLAT_RK_CCI_BASE
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/* Initialize CCI driver */
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cci_init(PLAT_RK_CCI_BASE, cci_map, ARRAY_SIZE(cci_map));
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#endif
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}
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void plat_cci_enable(void)
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{
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/*
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* Enable CCI coherency for this cluster.
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* No need for locks as no other cpu is active at the moment.
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*/
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#ifdef PLAT_RK_CCI_BASE
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cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
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#endif
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}
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void plat_cci_disable(void)
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{
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#ifdef PLAT_RK_CCI_BASE
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cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
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#endif
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}
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