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9fd9f1d024
RK3566/RK3568 is a Quad-core soc and Cortex-a55 inside. This patch supports the following functions: 1. basic platform setup 2. power up/off cpus 3. suspend/resume cpus 4. suspend/resume system 5. reset system Signed-off-by: shengfei Xu <xsf@rock-chips.com> Change-Id: I8b98a4d07664de26bd6078f63664cbc3d9c1c68c
46 lines
1.5 KiB
C
46 lines
1.5 KiB
C
/*
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* Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef DSU_DEF_H
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#define DSU_DEF_H
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#include <lib/utils_def.h>
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/********************************************************************
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* DSU Cluster Configuration registers definitions
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********************************************************************/
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#define CLUSTERCFR_EL1 S3_0_C15_C3_0
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#define CLUSTERCFR_ACP_SHIFT U(11)
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/********************************************************************
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* DSU Cluster Main Revision ID registers definitions
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********************************************************************/
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#define CLUSTERIDR_EL1 S3_0_C15_C3_1
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#define CLUSTERIDR_REV_SHIFT U(0)
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#define CLUSTERIDR_REV_BITS U(4)
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#define CLUSTERIDR_VAR_SHIFT U(4)
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#define CLUSTERIDR_VAR_BITS U(4)
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/********************************************************************
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* DSU Cluster Auxiliary Control registers definitions
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********************************************************************/
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#define CLUSTERACTLR_EL1 S3_0_C15_C3_3
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#define CLUSTERPWRCTLR_EL1 S3_0_C15_C3_5
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#define CLUSTERACTLR_EL1_DISABLE_CLOCK_GATING (ULL(1) << 15)
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#define CLUSTERACTLR_EL1_DISABLE_SCLK_GATING (ULL(3) << 15)
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/********************************************************************
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* Masks applied for DSU errata workarounds
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********************************************************************/
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#define DSU_ERRATA_936184_MASK (U(0x3) << 15)
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#ifndef __ASSEMBLER__
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void dsu_pwr_dwn(void);
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#endif
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#endif /* DSU_DEF_H */
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