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9fbdb80209
Currently the `tzc400_configure_region` and `tzc_dmc500_configure_region` functions uses uintptr_t as the data type for `region_top` and `region_base` variables, which will be converted to 32/64 bits for AArch32/AArch64 respectively. But the expectation is to keep these addresses at least 64 bit. This patch modifies the data types to make it at least 64 bit by using unsigned long long instead of uintptr_t for the `region_top` and `region_base` variables. It also modifies the associated macros `_tzc##fn_name##_write_region_xxx` accordingly. Change-Id: I4e3c6a8a39ad04205cf0f3bda336c3970b15a28b
174 lines
6 KiB
C
174 lines
6 KiB
C
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __TZC_DMC500_H__
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#define __TZC_DMC500_H__
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#include <tzc_common.h>
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#define SI_STATUS_OFFSET 0x000
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#define SI_STATE_CTRL_OFFSET 0x030
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#define SI_FLUSH_CTRL_OFFSET 0x034
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#define SI_INT_CONTROL_OFFSET 0x048
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#define SI_INT_STATUS_OFFSET 0x004
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#define SI_TZ_FAIL_ADDRESS_LOW_OFFSET 0x008
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#define SI_TZ_FAIL_ADDRESS_HIGH_OFFSET 0x00c
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#define SI_FAIL_CONTROL_OFFSET 0x010
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#define SI_FAIL_ID_OFFSET 0x014
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#define SI_INT_CLR_OFFSET 0x04c
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/*
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* DMC-500 has 2 system interfaces each having a similar set of regs
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* to configure each interface.
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*/
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#define SI0_BASE 0x0000
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#define SI1_BASE 0x0200
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/* Bit positions of SIx_SI_STATUS */
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#define SI_EMPTY_SHIFT 0x01
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#define SI_STALL_ACK_SHIFT 0x00
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#define SI_EMPTY_MASK 0x01
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#define SI_STALL_ACK_MASK 0x01
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/* Bit positions of SIx_SI_INT_STATUS */
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#define PMU_REQ_INT_OVERFLOW_STATUS_SHIFT 18
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#define FAILED_ACCESS_INT_OVERFLOW_STATUS_SHIFT 16
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#define PMU_REQ_INT_STATUS_SHIFT 2
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#define FAILED_ACCESS_INT_INFO_TZ_OVERLAP_STATUS_SHIFT 1
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#define FAILED_ACCESS_INT_STATUS_SHIFT 0
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#define PMU_REQ_INT_OVERFLOW_STATUS_MASK 0x1
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#define FAILED_ACCESS_INT_OVERFLOW_STATUS_MASK 0x1
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#define PMU_REQ_INT_STATUS_MASK 0x1
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#define FAILED_ACCESS_INT_INFO_TZ_OVERLAP_STATUS_MASK 0x1
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#define FAILED_ACCESS_INT_STATUS_MASK 0x1
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/* Bit positions of SIx_TZ_FAIL_CONTROL */
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#define DIRECTION_SHIFT 24
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#define NON_SECURE_SHIFT 21
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#define PRIVILEGED_SHIFT 20
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#define FAILED_ACCESS_INT_INFO_RANK_MASKED_SHIFT 3
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#define FAILED_ACCESS_INT_INFO_UNMAPPED_SHIFT 2
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#define FAILED_ACCESS_INT_TZ_FAIL_SHIFT 0x1
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#define FAILED_ACCESS_INT_INFO_OUTSIDE_DEFAULT_SHIFT 0
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#define DIRECTION_MASK 0x1
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#define NON_SECURE_MASK 0x1
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#define PRIVILEGED_MASK 0x1
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#define FAILED_ACCESS_INT_INFO_RANK_MASKED_MASK 0x1
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#define FAILED_ACCESS_INT_INFO_UNMAPPED_MASK 0x1
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#define FAILED_ACCESS_INT_TZ_FAIL_MASK 1
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#define FAILED_ACCESS_INT_INFO_OUTSIDE_DEFAULT_MASK 0x1
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/* Bit positions of SIx_FAIL_STATUS */
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#define FAIL_ID_VNET_SHIFT 24
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#define FAIL_ID_ID_SHIFT 0
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#define FAIL_ID_VNET_MASK 0xf
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#define FAIL_ID_ID_MASK 0xffffff
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/* Bit positions of SIx_SI_STATE_CONTRL */
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#define SI_STALL_REQ_GO 0x0
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#define SI_STALL_REQ_STALL 0x1
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/* Bit positions of SIx_SI_FLUSH_CONTROL */
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#define SI_FLUSH_REQ_INACTIVE 0x0
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#define SI_FLUSH_REQ_ACTIVE 0x1
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#define SI_FLUSH_REQ_MASK 0x1
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/* Bit positions of SIx_SI_INT_CONTROL */
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#define PMU_REQ_INT_EN_SHIFT 2
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#define OVERLAP_DETECT_INT_EN_SHIFT 1
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#define FAILED_ACCESS_INT_EN_SHIFT 0
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#define PMU_REQ_INT_EN_MASK 0x1
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#define OVERLAP_DETECT_INT_EN_MASK 0x1
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#define FAILED_ACCESS_INT_EN_MASK 0x1
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#define PMU_REQ_INT_EN 0x1
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#define OVERLAP_DETECT_INT_EN 0x1
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#define FAILED_ACCESS_INT_EN 0x1
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/* Bit positions of SIx_SI_INT_CLR */
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#define PMU_REQ_OFLOW_CLR_SHIFT 18
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#define FAILED_ACCESS_OFLOW_CLR_SHIFT 16
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#define PMU_REQ_INT_CLR_SHIFT 2
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#define FAILED_ACCESS_INT_CLR_SHIFT 0
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#define PMU_REQ_OFLOW_CLR_MASK 0x1
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#define FAILED_ACCESS_OFLOW_CLR_MASK 0x1
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#define PMU_REQ_INT_CLR_MASK 0x1
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#define FAILED_ACCESS_INT_CLR_MASK 0x1
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#define PMU_REQ_OFLOW_CLR 0x1
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#define FAILED_ACCESS_OFLOW_CLR 0x1
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#define PMU_REQ_INT_CLR 0x1
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#define FAILED_ACCESS_INT_CLR 0x1
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/* Macro to get the correct base register for a system interface */
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#define IFACE_OFFSET(sys_if) ((sys_if) ? SI1_BASE : SI0_BASE)
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#define MAX_SYS_IF_COUNT 2
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#define MAX_REGION_VAL 8
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/* DMC-500 supports striping across a max of 4 DMC instances */
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#define MAX_DMC_COUNT 4
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/* Consist of part_number_1 and part_number_0 */
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#define DMC500_PERIPHERAL_ID 0x0450
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/* Filter enable bits in a TZC */
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#define TZC_DMC500_REGION_ATTR_F_EN_MASK 0x1
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/* Length of registers for configuring each region */
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#define TZC_DMC500_REGION_SIZE 0x018
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#ifndef __ASSEMBLY__
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#include <stdint.h>
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/*
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* Contains the base addresses of all the DMC instances.
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*/
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typedef struct tzc_dmc500_driver_data {
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uintptr_t dmc_base[MAX_DMC_COUNT];
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int dmc_count;
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} tzc_dmc500_driver_data_t;
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void tzc_dmc500_driver_init(const tzc_dmc500_driver_data_t *plat_driver_data);
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void tzc_dmc500_configure_region0(tzc_region_attributes_t sec_attr,
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unsigned int nsaid_permissions);
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void tzc_dmc500_configure_region(int region_no,
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unsigned long long region_base,
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unsigned long long region_top,
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tzc_region_attributes_t sec_attr,
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unsigned int nsaid_permissions);
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void tzc_dmc500_set_action(tzc_action_t action);
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void tzc_dmc500_config_complete(void);
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int tzc_dmc500_verify_complete(void);
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#endif /* __ASSEMBLY__ */
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#endif /* __TZC_DMC500_H__ */
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