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dd53cfe19f
The revision register address will be changed in the next SoC. The LSI revision is needed in order to know where the revision register is located, but you need to read out the revision register for that. This is impossible. We need to know the revision register address by other means. Use BL_CODE_BASE, where the base address of the TF image that is currently running. If it is bigger than 0x80000000 (i.e. the DRAM base is 0x80000000), we assume it is a legacy SoC. Change-Id: I9d7f4325fe2085a8a1ab5310025e5948da611256 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
57 lines
1.1 KiB
C
57 lines
1.1 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/bl_common.h>
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#include <lib/mmio.h>
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#include "uniphier.h"
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#define UNIPHIER_REVISION 0x5f800000UL
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#define UNIPHIER_REVISION_NEW 0x1f800000UL
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static unsigned int uniphier_get_revision_field(unsigned int mask,
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unsigned int shift)
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{
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uintptr_t reg;
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if (BL_CODE_BASE >= 0x80000000UL)
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reg = UNIPHIER_REVISION;
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else
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reg = UNIPHIER_REVISION_NEW;
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return (mmio_read_32(reg) >> shift) & mask;
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}
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unsigned int uniphier_get_soc_type(void)
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{
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return uniphier_get_revision_field(0xff, 16);
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}
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unsigned int uniphier_get_soc_model(void)
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{
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return uniphier_get_revision_field(0x07, 8);
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}
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unsigned int uniphier_get_soc_revision(void)
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{
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return uniphier_get_revision_field(0x1f, 0);
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}
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unsigned int uniphier_get_soc_id(void)
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{
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uint32_t type = uniphier_get_soc_type();
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switch (type) {
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case 0x31:
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return UNIPHIER_SOC_LD11;
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case 0x32:
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return UNIPHIER_SOC_LD20;
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case 0x35:
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return UNIPHIER_SOC_PXS3;
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default:
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return UNIPHIER_SOC_UNKNOWN;
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}
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}
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